 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Application Note 78K/0 Series 8-bit Single-chip Microcontroller Basic (III) PD78054 subseries PD78064 subseries PD78078 subseries PD78083 subseries PD780018 subseries PD780058 subseries PD780308 subseries PD78058F subseries PD78064B subseries PD78075B subseries PD78098B subseries PD78054Y subseries PD78064Y subseries PD78078Y subseries PD78098 subseries PD780018Y subseries PD780058Y subseries PD780308Y subseries PD78058FY subseries PD78070A, 78070AY PD78075BY subseries Document No. U10182EJ2V0AN00 (2nd edition) Date Published October 1997 N (c) Printed in Japan 1995 [MEMO] NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M7 96.5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 Major Revisions in This Edition Page Throughout Description Addition of following products as target products: PD780018, 780018Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY PD78052(A), 78053(A), 78054(A) PD78062(A), 78063(A), 78064(A) PD78081(A), 78082(A), 78P083(A), 78081(A2) PD78058F(A), 78058FY(A) PD78064B(A) Deletion of following products as target products: PD78P054Y, 78P064Y, 78074, 78075, 78075, 78074Y, 78075Y p.100 p.113 p.196 p.197 p.204, p206 Addition of Note 2 and Caution 2 to Figure 4-5 Format of Watchdog Timer Mode Register Addition of Caution to Figure 5-8 Format of External Interrupt Mode Register 0 Addition of Table 8-2 Items Supported by Each Subseries Addition of Table 8-3 Registers of Serial Interface Addition of note on using wake-up function and note on changing operation mode to Figures 8-7 and 8-8 Format of Serial Operating Mode Register 0 p.218, p.224 Addition of Caution to Figures 8-16 and 8-17 Format of Automatic Data Transfer/Reception Interval Specification Register Addition of Figures 8-23 and 8-24 Format of Serial Interface Pin Select Register p.239 p.240 p.250 p.286 PD6252 as maintenance product in 8.1 Interface with EEPROMTM (PD6252) Addition of (5) Limitations when using I2C bus mode to 8.1.2 Communication in I2C bus mode Addition of (f) Limitations when using UART mode to 8.5 Interface in Asynchronous Serial Interface (UART) Mode Addition of Figure 11-3 Format of Port Mode Register 12 Description of following register formats and tables for each subseries: Figures 8-14 and 8-15 Format of Automatic Data Transmission/Reception Control Register Tables 8-4, 8-5, and 8-6 Setting of Operation Modes of Serial Interface Channel 2 Figures 12-1 and 12-2 Format of LCD Display Mode Register p.347 p.216, p.217 p.229-p.232 p.352, p.353 p.387 Addition of APPENDIX B REVISION HISTORY The mark shows major revised points. INTRODUCTION Readers This Application Note is intended for use by engineers who understand the functions of the 78K/0 series and wish to design application programs with the following subseries products: * Subseries PD78054 subseries : PD78052, 78053, 78054, 78P054, 78055, 78056, 78058, 78P058, 78052(A), 78053(A), 78054(A) PD78054Y subseries : PD78064 subseries : PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y, 78P058Y PD78062, 78063, 78064, 78P064, 78062(A), 78063(A), 78064(A) PD78064Y subseries : PD78078 subseries PD78083 subseries PD78098 subseries : : : PD78062Y, 78063Y, 78064Y PD78076, 78078, 78P078 PD78076Y, 78078Y, 78P078Y PD78081, 78082, 78P083, 78081(A), 78082(A), 78P83(A), 78081(A2) PD78078Y subseries : PD78094, 78095, 78096, 78098ANote 1, 78P098ANote 1 PD780018 subseries : PD780018Y subseries : PD780058 subseries : PD780058Y subseries : PD780016Note 2, 780018Note 2, 78P0018Note 2 PD780016YNote 2, 780018YNote 2, 78P0018YNote 2 PD780053Note 1, 780054Note 1, 780055Note 1, 780056Note 1, 780058Note 1, 78F0058Note 1 PD780053YNote 2, 780054YNote 2, 780055YNote 2, 780056YNote 2, 780058YNote 2, 78F0058YNote 2 PD780308 subseries : PD780308Y subseries : PD78058F subseries : PD78058FY subseries : PD78064B subseries : PD78070A, 78070AY PD78075B subseries : PD78075BY subseries: PD78098B subseries : PD780306Note 1, 780308Note 1, 78P0308Note 1 PD780306YNote 1, 780308YNote 1, 78P0308YNote 1 PD78056F, 78058F, 78P058F, 78058F(A) PD78056FY, 78058FY, 78P058FY, 78P058FY(A) PD78064B, 78P064B, 78064B(A) PD78074B, 78075B PD78074BYNote 1, 78075BYNote 1 PD78095BNote 2, 78096BNote 2, 78098BNote 2, 78P098BNote 2 Notes 1. Under development 2. Planned Remarks 1. The PD78052(A), 78053(A), and 78054(A) have higher reliability than the PD78052, 78053, and 78054. 2. The PD78062(A), 78063(A), and 78064(A) have higher reliability than the PD78062, 78063, and 78064. 3. The PD78081(A), 78082(A), 78P083(A), and 78081(A2) have higher reliability than the PD78081, 78082, and 78P083. 4. The PD78058F(A) and 78058FY(A) have higher reliability than the PD78058F and 78058FY. 5. The PD78064B(A) has higher reliability than the PD78064B. Purpose This Application Note is to deepen your understanding of the basic functions of the 78K/0 series by using program examples. Note that the programs and hardware configuration shown in this document are only examples and not subject to mass production. Organization This Application Note consists of the following contents: * General * Software * Hardware In addition to this Application Note, the following Application Notes are also available: Document Number Japanese English IEA-1288 Document Name 78K/0 Series Application Note Basic (I) 78K/0 Series Application Note Basic (II) Targeted Subseries Contents Explains basic functions of products in 78K/0 series by using program examples IEA-715 PD78002, 78002Y PD78014, 78014Y PD78018F, 78018FY U10121J U10121E PD78044 PD78044H PD780208 PD780228 78K/0 Series Application Note Basic (III) U10182J This document PD78054, 78054Y PD78064, 78064Y PD78078, 78078Y PD78083 PD78098 PD780018, 780018Y PD780058, 780058Y PD780308, 780308Y PD78058F, 78058FY PD78064B PD78070A, 78070AY PD78075B, 78075BY PD78098B 78K/0 Series Application Note Floating-Point Operation Program IEA-718 IEA-1289 All subseries in 78K/0 series except PD78002 and 78002Y subseries Explains floating-point operation programs of products in 78K/0 series PD78014 Series Application Note Electronic Pocketbook IEA-744 IEA-1301 PD78014 only PD78014 and 78P014 Explains how to organize electronic pocketbook by using PD78014 subseries Caution The application examples and program lists shown in this Application Note assume that the main system clock operates at 4.19 MHz, not at 5.0 MHz. How to Read This Manual Although this Application Note explains the functions of the 78K/0 series products, the functions of some products in each subseries differ from those of the others. (1/2) Subseries PD78054 PD78064 PD78078 PD78083 Chapter PD78054Y PD78064Y PD78078Y CHAPTER 1 GENERAL CHAPTER 2 FUNDAMENTALS OF SOFTWARE CHAPTER 3 APPLICATIONS OF SYSTEM CLOCK SELECTION CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER CHAPTER 5 APPLICATIONS OF - 16-BIT TIMER/EVENT COUNTER CHAPTER 6 APPLICATIONS OF - 8-BIT TIMER/EVENT COUNTER CHAPTER 7 APPLICATIONS OF - WATCH TIMER CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE CHAPTER 9 APPLICATIONS OF A/D CONVERTER CHAPTER 10 APPLICATIONS - - OF D/A CONVERTER CHAPTER 11 APPLICATION OF - - REAL-TIME OUTPUT PORT CHAPTER 12 APPLICATIONS - - - OF LCD CONTROLLER/DRIVER CHAPTER 13 APPLICATIONS - OF KEY INPUT PD78098 PD780018 PD780058 PD780018Y PD780058Y - - - - - (2/2) Subseries PD780308 PD78058F Chapter PD780308Y PD78058FY CHAPTER 1 GENERAL CHAPTER 2 FUNDAMENTALS OF SOFTWARE CHAPTER 3 APPLICATIONS OF SYSTEM CLOCK SELECTION CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER CHAPTER 7 APPLICATIONS OF WATCH TIMER CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE CHAPTER 9 APPLICATIONS OF A/D CONVERTER CHAPTER 10 APPLICATIONS - OF D/A CONVERTER CHAPTER 11 APPLICATION OF - REAL-TIME OUTPUT PORT CHAPTER 12 APPLICATIONS - OF LCD CONTROLLER/DRIVER CHAPTER 13 APPLICATIONS OF KEY INPUT PD78064B PD78070A PD78075B PD78098B PD78070AY PD78075BY - - - - - The (A)-model and standard models differ only in quality grade. The PD78081(A2) differs from standard models and (A)-models in terms of supply voltage and operating temperature range. For details, refer to the individual Data Sheet. In this document, read (A)-models and (A2)-model as follows: PD78052 PD78054 PD78063 PD78081 PD78052(A) PD78054(A) PD78063(A) PD78081(A) PD78053 PD78062 PD78064 PD78082 PD78081 PD78053(A) PD78062(A) PD78064(A) PD78082(A) PD78081(A2) PD78P083 PD78P083(A) PD78058F PD78058F(A) PD78064B PD78064B(A) Legend Data significance Low active Note Caution Remark PD78058FY PD78058FY(A) : Left: higher digit, right: lower digit : xxx (top bar over pin or signal name) : Description of Note in the text : Important information : Supplement Decimal ... xxxx Hexadecimal ... xxxxH Numeric representation : Binary ... xxxx or xxxxB Quality Grade * Standard PD78052, 78053, 78054, 78055, 78056, 78058, 78P058 PD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y, 78P058Y PD78062, 78063, 78064, 78P064 PD78062Y, 78063Y, 78064Y PD78076, 78078, 78P078 PD78076Y, 78078Y, 78P078Y PD78081, 78082, 78P083 PD78094, 78095, 78096, 78098A, 78P098A PD780016, 780018, 78P0018 PD780016Y, 780018Y, 78P0018Y PD780053, 780054, 780055, 780056, 780058, 78F0058 PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y, 78F0058Y PD780306, 780308, 78P0308 PD780306Y, 780308Y, 78P0308Y PD78056F, 78058F, 78P058F PD78056FY, 78058FY, 78P058FY PD78064B, 78P064B PD78070A, 78070AY PD78074B, 78075B PD78074BY, 78075BY PD78095B, 78096B, 78098B, 78P098B * Special PD78052(A), 78053(A), 78054(A) PD78062(A), 78063(A), 78064(A) PD78082(A), 78083(A), 78P083(A), 78081(A2) PD78058F(A), 78058FY(A) PD78064B(A) Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Application Field Related documents * Consumer appliances Some of the related documents listed below are preliminary versions but not so specified here. * Common related documents Document Number Document Name 78K/0 Series Application Note - Basic (III) 78K/0 Series Application Note - Floating-Point Operation Program 78K/0 Series User's Manual - Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table Japanese U10182J IEA-718 U12326J U10904J U10903J English This document IEA-1289 U12326E - - * Documents dedicated to product (1) PD78054 subseries Document Number Document Name Japanese English IC-3403 U12346E U10417E U11747E - U12171E PD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet PD78P054 Data Sheet PD78P058 Data Sheet PD78054, PD78054Y Subseries User's Manual PD78054 Subseries Special Function Register Table PD78052(A), 78053(A), 78054(A) Data Sheet (2) PD78054Y subseries U12327J U12346J IC-8884 U11747J U10102J U12171J Document Number Document Name Japanese English U10906E U10907E U11747E - PD78052Y, 78053Y, 78054Y, 78056Y, 78058Y Data Sheet PD78P058Y Data Sheet PD78054, 78054Y Subseries User's Manual PD78054Y Subseries Special Function Register Table (3) PD78064 subseries U10906J U10907J U11747J U10087J Document Number Document Name Japanese English U12338E U12589E U10335E U10105E - PD78062, 78063, 78064 Data Sheet PD78P064 Data Sheet PD78062(A), 78063(A), 78064(A) Data Sheet PD78064, 78064Y Subseries User's Manual PD78064 Subseries Special Function Register Table (4) PD78064Y subseries U12238J U12589J U10335J U10105J IEM-5568 Document Number Document Name Japanese U10330J U10105J IEM-5583 English U10330E U10105E - PD78062Y, 78063Y, 78064Y Data Sheet PD78064, 78064Y Subseries User's Manual PD78064Y Subseries Special Function Register Table (5) PD78078 subseries Document Number Document Name Japanese English U10167E U10168E U10641E - PD78076, 78078 Data Sheet PD78P078 Data Sheet PD78078 Subseries User's Manual PD78078 Subseries Special Function Register Table (6) PD78078Y subseries U10167J U10168J U10641J IEM-5607 Document Number Document Name Japanese English U10605E U10606E U10641E - PD78076Y, 78078Y Data Sheet PD78P078Y Data Sheet PD78078, 78078Y Subseries User's Manual PD78078Y Subseries Special Function Register Table (7) PD78083 subseries U10605J U10606J U10641J U10257J Document Number Document Name Japanese English U11415E U11006E To be released soon U12175E U12176E - PD78081, 78082 Data Sheet PD78P083 Data Sheet uPD78081(A), 78082(A) Data Sheet uPD78P083(A) Data Sheet U11415J U11006J U12436J U12175J U12176J IEM-5599 PD78083 Subseries User's Manual PD78083 Subseries Special Function Register Table (8) PD78098 subseries Document Name Document Number Japanese English U10146E U10203E IEU-1381 - PD78094, 78095, 78096, 78098A Data Sheet PD78P098A Data Sheet PD78098 Subseries User's Manual PD78098 Subseries Special Function Register List U10146J U10203J IEU-854 IEM-5591 (9) PD780018 subseries Document Number Document Name Japanese English Plan to prepare Plan to prepare Plan to prepare PD780016, 780018 Preliminary Product Information PD78P0018 Preliminary Product Information PD780018, 780018Y Subseries User's Manual (10) PD780018Y subseries Plan to prepare Plan to prepare Plan to prepare Document Number Document Name Japanese English U11810E Plan to prepare Plan to prepare PD780016Y, 780018Y Preliminary Product Information PD78P0018Y Preliminary Product Information PD780018, 780018Y Subseries User's Manual U11810J Plan to prepare Plan to prepare (11) PD780058 subseries Document Number Document Name Japanese English U12182E PD780053, 780054, 780055, 780056, 780058 Preliminary Product Information U12182J PD78F0058 Preliminary Product Information PD780058, 780058Y Subseries User's Manual U12092J U12013J U12092E U12013E (12) PD780058, 780058Y subseries Document Number Document Name Japanese English Plan to prepare PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y Preliminary Product Information Plan to prepare PD78F0058Y Preliminary Product Information PD780058, 780058Y Subseries User's Manual U12324J U12013J U12324E U12013E (13) PD780308 subseries Document Number Document Name Japanese English U11105E U11776E U11377E PD780306, 780308 Data Sheet PD78P0308 Preliminary Product Information PD780308, 780308Y Subseries User's Manual U11105J U11776J U11377J (14) PD780308Y subseries Document Number Document Name Japanese English U12251E U11832E U11377E PD780306Y, 780308Y Data Sheet PD78P0308Y Preliminary Product Information PD780308, 780308Y Subseries User's Manual U12251J U11832J U11377J (15) PD78058F subseries Document Number Document Name Japanese U11795J U11796J To be released soon U12068J English U11795E U11796E Plan to prepare U12068E PD78056F, 78058F Data Sheet PD78P058F Data Sheet PD78058F(A) Data Sheet PD78058F, 78058FY Subseries User's Manual (16) PD78058FY subseries Document Number Document Name Japanese English U12142E U12076E To be released soon PD78056FY, 78058FY Data Sheet PD78P058FY Data Sheet PD78058F, 78058FY Subseries User's Manual U12142J U12076J U12068J (17) PD78064B subseries Document Number Document Name Japanese English U11590E U11597E U11598E U10785E PD78064B Data Sheet PD78064B(A) Data Sheet PD78P064B Data Sheet PD780308, 780308Y User's Manual U11590J U11597J U11598J U10785J (18) PD78070A, 78070AY subseries Document Number Document Name Japanese English U10326E U10542E U10200E - - PD78070A Data Sheet PD78070AY Data Sheet PD78070A, 78070AY User's Manual PD78070A PD78070AY U10326J U10542J IEU-907 U10133J U10134J (19) PD78075B subseries Document Name Document Number Japanese English U12017E To be released soon PD78074B, 78075B Data Sheet PD78075B, 78075BY Subseries User's Manual U12017J U12560J (20) PD78075BY subseries Document Number Document Name Japanese English Plan to prepare To be released soon PD78074BY, 78075BY Data Sheet PD78075B, 78075BY Subseries User's Manual Plan to prepare U12560J (21) PD78098B subseries Document Number Document Name Japanese English Plan to prepare Plan to prepare Plan to prepare PD78095B, 78096B, 78098B Data Sheet PD78P098B Data Sheet PD78098B Subseries User's Manual Plan to prepare Plan to prepare To be released soon The contents of the above related documents are subject to change without notice. Be sure to use the latest edition when you design your system. CONTENTS CHAPTER 1 GENERAL ................................................................................................................... 1.1 Product Development of 78K/0 Series ....................................................................... 1.2 Features of 78K/0 Series .............................................................................................. CHAPTER 2 FUNDAMENTALS OF SOFTWARE .......................................................................... 2.1 Data Transfer .................................................................................................................. 2.2 Data Comparison ........................................................................................................... 2.3 Decimal Addition ........................................................................................................... 2.4 Decimal Subtraction ...................................................................................................... 2.5 Binary-to-Decimal Conversion ..................................................................................... 2.6 Bit Manipulation Instruction ......................................................................................... 2.7 Binary Multiplication (16 bits x 16 bits) ..................................................................... 2.8 Binary Division (32 bits / 16 bits) ............................................................................... CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION ................................................. 3.1 Changing PCC Immediately after RESET ................................................................... 3.2 Selecting Power ON/OFF .............................................................................................. CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER ............................................................... 4.1 Setting Watchdog Timer Mode .................................................................................... 4.2 Setting Interval Timer Mode ......................................................................................... CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ......................................... 5.1 Setting of Interval Timer ............................................................................................... 5.2 PWM Output .................................................................................................................... 5.3 Remote Controller Signal Reception .......................................................................... 5.3.1 5.3.2 Remote controller signal reception by counter clearing ................................................ Remote controller signal reception by PWM output and free running mode ................ 1 1 3 57 57 58 59 66 68 70 71 75 79 89 91 95 101 103 105 116 118 121 123 137 5.4 5.5 One-Shot Pulse Output ................................................................................................. PPG Output ..................................................................................................................... 152 156 163 171 172 173 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER ........................................... 6.1 Setting of Interval Timer ............................................................................................... 6.1.1 6.1.2 Setting of 8-bit timers ...................................................................................................... Setting of 16-bit timer ...................................................................................................... 6.2 Musical Scale Generation ............................................................................................. 174 181 187 195 240 242 250 CHAPTER 7 APPLICATIONS OF WATCH TIMER ........................................................................ 7.1 Watch and LED Display Program ................................................................................ CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE .............................................................. 8.1 Interface with EEPROMTM (PD6252) ......................................................................... 8.1.1 8.1.2 Communication in 2-wire serial I/O mode ...................................................................... Communication in I2 C bus mode .................................................................................... -i- 8.2 8.3 Interface with OSD LSI (PD6451A) ............................................................................ Interface in SBI Mode .................................................................................................... 8.3.1 8.3.2 Application as master CPU ............................................................................................. Application as slave CPU ................................................................................................ Application as master CPU ............................................................................................. Application as slave CPU ................................................................................................ 260 265 267 276 8.4 Interface in 3-Wire Serial I/O Mode ............................................................................. 8.4.1 8.4.2 279 280 283 8.5 Interface in Asynchronous Serial Interface (UART) Mode ...................................... 286 299 307 316 326 332 337 338 345 348 351 360 366 373 379 387 CHAPTER 9 APPLICATIONS OF A/D CONVERTER ................................................................... 9.1 Level Meter ..................................................................................................................... 9.2 Thermometer .................................................................................................................. 9.3 Analog Key Input ........................................................................................................... 9.4 4-Channel Input A/D Conversion ................................................................................. CHAPTER 10 APPLICATIONS OF D/A CONVERTER ................................................................. 10.1 SIN Wave Output ............................................................................................................ CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT ................................................... 11.1 Stepping Motor ............................................................................................................... CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER ............................................... 12.1 Static Display ................................................................................................................. 12.2 4-Time Division Display ................................................................................................ CHAPTER 13 APPLICATIONS OF KEY INPUT ............................................................................ APPENDIX A DESCRIPTION OF SPD CHART ............................................................................. APPENDIX B REVISION HISTORY ............................................................................................... - ii - LIST OF FIGURES (1/6) Fig. No. 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 1-10. 1-11. 1-12. 1-13. 1-14. 1-15. 1-16. 1-17. 1-18. 1-19. 1-20. 1-21. 1-22. 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 3-1. Title Block Diagram of PD78054 Subseries ....................................................................................... Block Diagram of PD78054Y Subseries .................................................................................... Block Diagram of PD78064 Subseries ....................................................................................... Block Diagram of PD78064Y Subseries .................................................................................... Block Diagram of PD78078 Subseries ....................................................................................... Block Diagram of PD78078Y Subseries .................................................................................... Block Diagram of PD78083 Subseries ....................................................................................... Block Diagram of PD78098 Subseries ....................................................................................... Block Diagram of PD780018 Subseries ..................................................................................... Block Diagram of PD780018Y Subseries .................................................................................. Block Diagram of PD780058 Subseries ..................................................................................... Block Diagram of PD780058Y Subseries .................................................................................. Block Diagram of PD780308 Subseries ..................................................................................... Block Diagram of PD780308Y Subseries .................................................................................. Block Diagram of PD78058F Subseries .................................................................................... Block Diagram of PD78058FY Subseries .................................................................................. Block Diagram of PD78064B Subseries .................................................................................... Block Diagram of PD78070A ..................................................................................................... Block Diagram of PD78070AY ................................................................................................... Block Diagram of PD78075B Subseries .................................................................................... Block Diagram of PD78075BY Subseries .................................................................................. Block Diagram of PD78098B Subseries .................................................................................... Data Exchange ............................................................................................................................ Data Comparison ......................................................................................................................... Decimal Addition .......................................................................................................................... Decimal Subtraction ..................................................................................................................... Binary-to-Decimal Conversion ..................................................................................................... Bit Operation ................................................................................................................................ Binary Multiplication ..................................................................................................................... Binary Division ............................................................................................................................. Format of Processor Clock Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A,78070AY) .................... Page 4 7 10 12 14 16 18 20 23 26 29 32 35 37 39 42 45 47 49 51 53 55 57 58 59 66 68 70 71 75 81 82 83 84 3-2. 3-3. 3-4. 3-5. Format of Processor Clock Control Register (PD78083 subseries) ........................................... Format of Processor Clock Control Register (PD78098, 78098B subseries) ............................ Format of Processor Clock Control Register (PD780018, 780018Y subseries) ........................ Format of Oscillation Mode Select Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ..................................................................................................................................... 85 85 3-6. Format of Oscillation Mode Select Register (PD78098, 78098B subseries) ............................. - iii - LIST OF FIGURES (2/6) Fig. No. 3-7. 3-8. 3-9. 3-10. 3-11. 3-12. 4-1. Title Format of Oscillation Mode Select Register (PD780018, 780018Y subseries) ............................................................................................... Format of Clock Select Register 1 (PD78098, 78098B subseries) ............................................ Format of Clock Select Register 2 (PD78098, 78098B subseries) ............................................ Example of Selecting CPU Clock after RESET (with PD78054 subseries) ............................... Example of System Clock Changing Circuit ................................................................................ Example of Changing System Clock on Power Failure (PD78054 subseries) ........................... Format of Timer Clock Select Register 2 (PD78054 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ................... Page 86 86 86 89 90 90 96 97 98 99 100 103 4-2. 4-3. 4-4. 4-5. 4-6. 5-1. Format of Timer Clock Select Register 2 (PD78083 subseries) ................................................ Format of Timer Clock Select Register 2 (PD78098, 78098B subseries) .................................. Format of Timer Clock Select Register 2 (PD780018, 780018Y subseries) .............................. Format of Watchdog Timer Mode Register .................................................................................. Count Timing of Watchdog Timer ................................................................................................ Format of Timer Clock Select Register 0 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ................................. 5-2. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. Format of Timer Clock Select Register 0 (PD78098, 78098B subseries) .................................. Format of Timer Clock Select Register 0 (PD780018, 780018Y subseries) .............................. Format of 16-Bit Timer Mode Control Register ............................................................................ Format of Capture/Compare Control Register ............................................................................. Format of 16-Bit Timer Output Control Register .......................................................................... Format of Port Mode Register 3 ................................................................................................... Format of External Interrupt Mode Register 0 .............................................................................. Format of Sampling Clock Select Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ................... 5-10. 5-11. 5-12. 5-13. 5-14. 5-15. 5-16. 5-17. 6-1. Format of Sampling Clock Select Register (PD78098, 78098B subseries) ............................... Format of Sampling Clock Select Register (PD780018, 780018Y subseries) ........................... Example of Remote Controller Signal Receiver Circuit ............................................................... Remote Controller Signal Transmitter IC Output Signal .............................................................. Output Signal of Receiver Preamplifier ........................................................................................ Sampling of Remote Controller Signal ......................................................................................... Timing of One-Shot Pulse Output Operation by Software Trigger ............................................... PPG Output Waveform Changing Timing .................................................................................... Format of Timer Clock Select Register 1 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ................... 6-2. Format of Timer Clock Select Register 1 (PD78098, 78098B subseries) .................................. 164 166 114 115 115 121 122 122 123 153 156 106 108 109 110 111 112 113 113 - iv - LIST OF FIGURES (3/6) Fig. No. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 7-1. Title Format of Timer Clock Select Register 1 (PD780018, 780018Y subseries) .............................. Format of 8-Bit Timer Mode Control Register .............................................................................. Format of 8-Bit Timer Output Control Register ............................................................................ Format of Port Mode Register 3 ................................................................................................... Count timing of 8-Bit Timers ........................................................................................................ Musical Scale Generation Circuit ................................................................................................. Timer Output and Interval ............................................................................................................ Format of Timer Clock Select Register 2 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ................... Page 167 168 169 170 171 174 174 182 183 184 7-2. 7-3. 7-4. Format of Timer Clock Select Register 2 (PD78098, 78098B subseries) .................................. Format of Timer Clock Select Register 2 (PD780018, 780018Y subseries) .............................. Format of Watch Timer Mode Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ..................................................................................................................................... 185 186 187 188 188 7-5. 7-6. 7-7. 7-8. 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. Format of Watch Timer Mode Control Register (PD78098, 78098B subseries) ........................ Concept of Watch Data ................................................................................................................ LED Display Timing ...................................................................................................................... Circuit Example of Watch Timer .................................................................................................. Format of Timer Clock Select Register 3 (PD78054, 78078, 780058, 78058F, 78075B subseries, PD78070A) ..................................... Format of Timer Clock Select Register 3 (PD78054Y, 78078Y, 780058Y, 78058FY, 78075BY subseries, PD78070AY) ....................... Format of Timer Clock Select Register 3 (PD78064, 780308, 78064B subseries) .................... Format of Timer Clock Select Register 3 (PD78064Y, 780308Y subseries) ............................. Format of Timer Clock Select Register 3 (PD78098, 78098B subseries) .................................. Format of Timer Clock Select Register 3 (PD780018, 780018Y subseries) .............................. Format of Serial Operating Mode Register 0 (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A) .................................................................................................. 198 199 200 201 202 203 204 8-8. Format of Serial Operating Mode Register 0 (PD78054Y, 78064Y, 78078Y, 780058Y, 780308, 78058FY, 78075BY subseries, PD78070AY) .............................................................................................................................. 8-9. Format of Serial Bus Interface Control Register (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A) ............................................................................................................... 8-10. Format of Serial Bus Interface Control Register (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, 206 208 PD78070AY) .............................................................................................................................. 210 -v- LIST OF FIGURES (4/6) Fig. No. 8-11. Title Format of Interrupt Timing Specification Register (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A) .................................................................................................. Page 212 8-12. Format of Interrupt Timing Specification Register (PD78054Y, 78064Y, 78078Y, 780058Y, 78008Y, 78058FY, 78075BY subseries, PD78070AY) .............................................................................................................................. 8-13. Format of Serial Operating Mode Register 1 (PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) ................................. 8-14. Format of Automatic Data Transfer/Reception Control Register (PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) ................................................................ 8-15. 8-16. Format of Automatic Data Transfer/Reception Control Register (PD780058, 780058Y subseries) ............................................................................................... Format of Automatic Data Transfer/Reception Interval Specification Register (PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY subseries, PD78070A, 78070AY) ............................................... 8-17. 8-18. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78098, 78098B subseries) ................................................................................................... Format of Serial Operating Mode Register 2 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, 213 215 216 217 218 224 PD78070A, 78070AY) ................................................................................................................ 8-19. Format of Asynchronous Serial Interface Mode Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, 227 PD78070A, 78070AY) ................................................................................................................ 8-20. Format of Asynchronous Serial Interface Status Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, 228 PD78070A, 78070AY) ................................................................................................................ 8-21. Format of Baud Rate Generator Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ..................................................................................................................................... 8-22. 8-23. 8-24. 8-25. 8-26. 8-27. 8-28. Format of Baud Rate Generator Control Register (PD78098, 78098B subseries) .................... Format of Serial Interface Pin Select Register (PD780058 and 780058Y Subseries) ............... Format of Serial Interface Pin Select Register (PD780308 and 780308Y Subseries) ........................................................................................ Pin Configuration of PD6252 ..................................................................................................... Example of Connection of PD6252 ............................................................................................ Communication Format of PD6252 ............................................................................................ Example of Connection between PD6252 and I2C Bus Mode ................................................... 234 235 237 239 239 240 242 243 250 - vi - LIST OF FIGURES (5/6) Fig. No. 8-29. 8-30. 8-31. 8-32. 8-33. 8-34. 8-35. 8-36. 8-37. 8-38. 8-39. 8-40. 8-41. 8-42. 8-43. 9-1. Title Page 251 260 260 265 266 267 267 279 279 283 288 289 289 295 296 PD6252 Operation Timing ........................................................................................................ Example of Connecting PD6451A ............................................................................................. Communication Format of PD6451A ......................................................................................... Example of Connection in SBI Mode ........................................................................................... Communication Format in SBI Mode ........................................................................................... ACK Signal in Case of Time out .................................................................................................. Testing Bus Line .......................................................................................................................... Example of Connection in 3-Wire Serial I/O Mode ...................................................................... Communication Format in 3-Wire Serial I/O Mode ...................................................................... Output of Busy Signal .................................................................................................................. Communication Block Diagram .................................................................................................... Communication Format ................................................................................................................ Reception Format ........................................................................................................................ Timing of Reception Completion Interrupt (when ISRM = 1) ....................................................... Receive Buffer Register Reading Disabled Period ...................................................................... Format of A/D Converter Mode Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) ..................................................................................................................................... 300 301 302 303 9-2. 9-3. 9-4. 9-5. Format of A/D Converter Mode Register (PD78098, 78098B subseries) .................................. Format of A/D Converter Mode Register (PD780018, 780018Y subseries) .............................. Format of A/D Converter Input Select Register ........................................................................... Format of External Interrupt Mode Register 1 .............................................................................. (PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) ................................................................ 304 305 306 306 307 307 308 316 317 327 332 337 338 338 340 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 10-1. 10-2. 10-3. 10-4. Format of External Interrupt Mode Register 1 (PD78064, 78064Y, 780058, 780058Y, 780308, 780308Y, 78064B subseries) ........................ Format of External Interrupt Mode Register 1 (PD78083 subseries) ......................................... Format of A/D Current Cut Select Register (PD78098, 78098B subseries) .............................. Example of Level Meter Circuit .................................................................................................... A/D Conversion Result and Display ............................................................................................. Concept of Peak Hold .................................................................................................................. Circuit Example of Thermometer ................................................................................................. Temperature vs. Output Characteristic ........................................................................................ Example of Analog Key Input Circuit ........................................................................................... Timing Chart in 4-Channel Scan Mode ........................................................................................ Format of D/A Converter Mode Register ..................................................................................... Analog Output and Output Data Storage Timing ......................................................................... D/A Output Waveform .................................................................................................................. SIN Wave Conversion Circuit ...................................................................................................... - vii - LIST OF FIGURES (6/6) Fig. No. 11-1. 11-2. 11-3. 11-4. 12-1. 12-2. 12-3. 12-4. 12-5. 12-6. 12-7. 12-8. 12-9. 12-10. 12-11. 12-12. 12-13. 12-14. 13-1. Title Format of Real-Time Output Port Mode Register ........................................................................ Format of Real-Time Output Port Control Register ...................................................................... Format of Port Mode Register 12 ................................................................................................. Phase Excitation Output Pattern and Output Timing ................................................................... Format of LCD Display Mode Register (PD78064, 78064Y, 78064B subseries) ....................... Format of LCD Display Mode Register (PD780308, 780308Y subseries) ................................. Format of LCD Display Control Register ...................................................................................... Relations between Contents of LCD Display Data Memory and Segment/Common Output ....... Common Signal Waveform .......................................................................................................... Phase Difference in Voltage between Command Signal and Segment Signal ............................ Display Pattern and Electrode Wiring of Static LCD .................................................................... Connection of Static LCD ............................................................................................................. Example of Connecting LCD Driving Power in Static Display Mode (with external divider resistor, VDD = 5 V, and VLCD = 5 V) ........................................................... Example of Static LCD Driving Waveform ................................................................................... Display Pattern of 4-Time Division LCD and Electrode Wiring .................................................... Connections of 4-Time Division LCD Panel ................................................................................. Example of Connecting LCD Drive Power in 4-Time Division Mode (with external divider resistor, VDD = 5 V, VLCD = 5 V) .................................................................. Example of 4-Time Division LCD Driving Waveform .................................................................... Key Matrix Circuit ......................................................................................................................... Page 346 346 347 348 352 353 354 356 358 359 360 361 361 362 366 367 367 368 373 - viii - LIST OF TABLES (1/2) Table. No. 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 1-10. 1-11. 1-12. 1-13. 1-14. 1-15. 1-16. 1-17. 1-18. 1-19. 1-20. 1-21. 1-22. 3-1. 3-2. 3-3. 5-1. 5-2. 6-1. 8-1. 8-2. 8-3. 8-4. Title Functional Outline of PD78054 Subseries ................................................................................. Functional Outline of PD78054Y Subseries ............................................................................... Functional Outline of PD78064 Subseries ................................................................................. Functional Outline of PD78064Y Subseries ............................................................................... Functional Outline of PD78078 Subseries ................................................................................. Functional Outline of PD78078Y Subseries ............................................................................... Functional Outline of PD78083 Subseries ................................................................................. Functional Outline of PD78098 Subseries ................................................................................. Functional Outline of PD780018 Subseries ............................................................................... Functional Outline of PD780018Y Subseries ............................................................................. Functional Outline of PD780058 Subseries ............................................................................... Functional Outline of PD780058Y Subseries ............................................................................. Functional Outline of PD780308 Subseries ............................................................................... Functional Outline of PD780308Y Subseries ............................................................................. Functional Outline of PD78058F Subseries ............................................................................... Functional Outline of PD78058FY Subseries ............................................................................ Functional Outline of PD78064B Subseries ............................................................................... Functional Outline of PD78070A ................................................................................................ Functional Outline of PD78070AY ............................................................................................. Functional Outline of PD78075B8 Subseries ............................................................................. Functional Outline of PD78075BY Subseries ............................................................................ Functional Outline of PD78098B Subseries ............................................................................... Maximum Time Required for Changing CPU Clock ..................................................................... Relation between CPU Clock and Minimum Instruction Execution Time (other than PD78098 and 78098B subseries) ............................................................................ CPU Clock (fCPU) List (PD78098 and 78098B Subseries) .......................................................... Valid Time of Input Signal ............................................................................................................ Valid Time of Input Signal ............................................................................................................ Musical Scale and Frequency ...................................................................................................... Serial Interface Channel of Each Subseries ................................................................................ Items Supported by Each Subseries ............................................................................................ Registers of Serial Interface ......................................................................................................... Setting of Operation Modes of Serial Interface Channel 2 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) ................................... Page 5 8 11 13 15 17 19 21 24 27 30 33 36 38 40 43 46 48 50 52 54 56 80 87 88 123 137 17 195 196 197 229 230 232 8-5. 8-6. Setting of Operation Modes of Serial Interface Channel 2 (PD780058 and 780058Y Subseries) .................................................................................................................... Setting of Operation Modes of Serial Interface Channel 2 (PD780308 and 780308Y Subseries) .................................................................................................................... - ix - LIST OF TABLES (2/2) Table. No. 8-7. 8-8. 8-9. 8-10. 9-1. 9-2. 9-3. 10-1. 11-1. 12-1. 12-2. 12-3. 12-4. A-1. Title Pin Function of PD6252 ............................................................................................................. Page 241 242 266 287 318 326 327 339 346 355 357 360 366 379 PD6252 Commands ................................................................................................................... Signals in SBI Mode ..................................................................................................................... Relations between Main System Clock and Baud Rate (at fX = 4.19 MHz) ................................. A/D Conversion Value and Temperature ..................................................................................... Input Voltage and Key Code ........................................................................................................ Resistances of R1 through R5 ..................................................................................................... Voltage of SIN Wave Output and Preset Value ........................................................................... Operation Mode and Output Trigger of Real-Time Output Port ................................................... Maximum Number of Pixels for Display ....................................................................................... COM Signal .................................................................................................................................. Select and Unselect Voltages (COM0) ........................................................................................ Select and Unselect Voltages (COM0, 1, 2, 3) ............................................................................ Comparison between SPD Symbols and Flowchart Symbol ....................................................... -x- CHAPTER 1 GENERAL 1.1 Product Development of 78K/0 Series The following shows the products organized according to usage. The names in the parallelograms are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 Inverter control PD78075BY PD78078Y PD78070AY PD780018AY PD780058YNote PD78058FY PD78054Y PD780034Y PD780024Y PD78018FY PD78014Y PD78002Y EMI-noise reduced version of the PD78078 A timer was added to the PD78054 and external interface was enhanced ROM-less version of the PD78078 Serial I/O of the PD78078Y was enhanced and the function is limited. Serial I/O of the PD78054 was enhanced and EMI-noise was reduced. EMI-noise reduced version of the PD78054 UART and D/A converter were enhanced to the PD78014 and I/O was enhanced A/D converter of the PD780024 was enhanced Serial I/O of the PD78018F was added and EMI-noise was reduced. EMI-noise reduced version of the PD78018F Low-voltage (1.8 V) operation version of the PD78014, with larger selection of ROM and RAM capacities An A/D converter and 16-bit timer were added to the PD78002 An A/D converter was added to the PD78002 Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) 64-pin 64-pin PD780964 PD780924 FIPTM drive A/D converter of the PD780924 was enhanced On-chip inverter control circuit and UART. EMI-noise was reduced. 100-pin 100-pin 78K/0 Series 80-pin 80-pin PD780208 PD780228 PD78044H PD78044F LCD drive The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 An N-ch open drain I/O was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34 100-pin 100-pin 100-pin PD780308 PD78064B PD78064 PD780308Y PD78064Y The SIO of the PD78064 was enhanced, and ROM, RAM capacity increased EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, On-chip UART IEBusTM supported 80-pin 80-pin PD78098B PD78098 Meter control EMI-noise reduced version of the PD78098 An IEBus controller was added to the PD78054 80-pin PD780973 LV On-chip automobile meter driving controller/driver 64-pin PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter Note Under planning 1 CHAPTER 1 GENERAL The following lists the main functional differences between subseries products. Function Subseries Name Control ROM Capacity 32K-40K 48K-60K - 24K-60K 48K-60K 16K-60K 8K-32K - 8ch 8ch - - 3ch (UART: 1ch, time division 3-wire: 1ch) 2ch 8K-60K 8K-32K 8K 8K-16K - - 1ch - 8K-32K 3ch Note - 1ch - 8ch - 8ch 32K-60K 48K-60K 32K-48K 16K-40K 48K-60K 32K 16K-32K 40K-60K 32K-60K 24K-32K 3ch 1ch 1ch 1ch 5ch - - 2ch (UART: 1ch) 56 4.5 V - 2ch 1ch 1ch 1ch 8ch - 2ch 3ch (UART: 1ch) 69 2.7 V 2ch 1ch 1ch 1ch 8ch - - 2ch 1ch 3ch - 1ch 1ch 8ch - 1ch 2ch 3ch (time division UART: 1ch) 2ch (UART: 1ch) 57 2.0 V - 8ch - - - 2ch 1ch 74 72 68 2.7 V 4.5 V 2.7 V - - 1ch (UART: 1ch) 2ch (UART: 2ch) 1ch 39 53 33 47 1.8 V 2.7 V - 2.7 V - 51 2ch 2ch 3ch (time division UART: 1ch) 3ch (UART: 1ch) 61 68 69 2.7 V 1.8 V 2.7 V 2.0 V 1.8 V 8-bit 10-bit 8-bit 8-bit 16-bit Watch WDT A/D A/D D/A 4ch 1ch 1ch 1ch 8ch - Timer Serial Interface I/O 88 VDD MIN. External Value Expansion 1.8 V PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 2ch 3ch (UART: 1ch) 53 1.8 V Inverter control FIP drive PD780964 PD780924 PD780208 PD780228 PD78044H PD78044F 2ch 1ch LCD drive PD780308 PD78064B PD78064 IEBus PD78098 supported PD78098B Meter control LV PD780973 PD78P0914 32K 6ch - - 1ch 8ch - - 2ch 54 4.5 V Note 10-bit timer: 1 channel 2 CHAPTER 1 GENERAL 1.2 Features of 78K/0 Series The 78K/0 series is a collection of 8-bit single-chip microcontrollers ideal for commercial systems. The PD78054 and 78054Y subseries are provided with peripheral hardware functions such as an A/D converter, D/A converter, timer, serial interface, real-time output port, and interrupt function. The PD78064 and 78064Y subseries are provided with peripheral hardware functions such as an LCD controller/ driver, A/D converter, timer, serial interface, and interrupt function. The PD78078 and 78078Y subseries are based on the PD78054 and 78054Y subseries with a timer added and the external interface function reinforced. The PD78083 subseries is provided with peripheral hardware functions such as an A/D converter, timer, serial interface, and interrupt function. The PD78098 subseries is based on the PD78054 subseries with an IEBus controller added. The PD780018 and 780018Y subseries are versions of the PD78078 and 78078Y subseries (serial interface with time division transfer function) with an improved serial interface and a limited number of functions. The PD780058 and 780058Y subseries are low-EMI noise versions of the PD78054 and 78054Y subseries (serial interface with time division transfer function), with an improved serial interface. The PD780308 and 780308Y subseries are versions of the PD78064 and 78064Y subseries with increased ROM and RAM with an improved serial interface. The PD78058F, 78058FY, 78064B, 78075B, 78075BY, and 78098B subseries are low-EMI noise versions of the PD78054, 78054Y, 78064, 78078, 78078Y, and 78098 subseries. The PD78070A and 78070AY subseries are the ROM-less versions of the PD78078 and 78078Y subseries. The PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries and PD78070AY are provided with I2C bus control function instead of the SBI function of the PD78054, 78064, 78078, 780058, 780308, 78058F, 78075B subseries and PD78070A. In addition, one-time PROM, EPROM, or flash-memory models that can operate at the same operating voltage as the mask ROM models and that are ideal for early and small-scale production of the application system are also available. The block diagram and function outline of each series is shown on the following pages. 3 CHAPTER 1 GENERAL Figure 1-1. Block Diagram of PD78054 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 P00 P01-P06 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 PORT3 WATCHDOG TIMER PORT4 P30-P37 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 P40-P47 SERIAL INTERFACE 0 PORT5 78K/0 CPU CORE ROM PORT6 P50-P57 P60-P67 SERIAL INTERFACE 1 PORT7 P70-P72 PORT12 SERIAL INTERFACE 2 RAM PORT13 P120-P127 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): PD78P054, 78P058 4 CHAPTER 1 GENERAL Table 1-1. Functional Outline of PD78054 Subseries (1/2) Item Part Number Internal memory ROM Mask ROM 16K bytes High-speed RAM Buffer RAM 24K bytes PD78052 PD78053 PD78054 PD78P054 Note 1 PD78055 PD78056 PD78058 PD78P058 Note 2 PROM 32K bytes 32K bytesNote 2 Mask ROM 40K bytes 48K bytes PROM 60K bytes 60K bytesNote 3 1024 bytesNote 3 512 bytes 1024 bytes 32 bytes 1024 bytesNote 3 1024 bytes Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) 1024 bytes 1024 bytesNote 4 instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 69 2 63 4 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The PD78P054 is a PROM model of the PD78052, 78053, and 78054. 2. The PD78P058 is a PROM model of the PD78055, 78056, and 78058. 3. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS). 4. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). 5 CHAPTER 1 GENERAL Table 1-1. Functional Outline of PD78054 Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software PD78052 PD78053 PD78054 PD78P054 Note 1 PD78055 PD78056 PD78058 PD78P058 Note 2 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 6.0 V * 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) * 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)Note 3 * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) (PD78052, 78053, 78054, 78P054, 78058 only) * 80-pin ceramic WQFN (14 x 14 mm) (PD78P054, 78P058 only) Notes 1. The PD78P054 is a PROM model of the PD78052, 78053, and 78054. 2. The PD78P058 is a PROM model of the PD78055, 78056, and 78058. 3. Under planning 6 CHAPTER 1 GENERAL Figure 1-2. Block Diagram of PD78054Y Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 P00 P01-P06 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 PORT3 WATCHDOG TIMER PORT4 P30-P37 WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 P40-P47 SERIAL INTERFACE 0 PORT5 78K/0 CPU CORE ROM PORT6 P50-P57 P60-P67 SERIAL INTERFACE 1 PORT7 P70-P72 PORT12 SERIAL INTERFACE 2 RAM PORT13 P120-P127 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The capacities of the internal ROM and RAM differ depending on the model. 2. ( ): PD78P058Y 7 CHAPTER 1 GENERAL Table 1-2. Functional Outline of PD78054Y Subseries (1/2) Item Part Number Internal memory ROM PD78052Y Mask ROM 16K bytes PD78053Y PD78054Y PD78055Y PD78056Y PD78058Y PD78P058Y PROM 24K bytes 1024 bytes 32K bytes 40K bytes 48K bytes 60K bytes 60K bytesNote 1 1024 bytesNote 1 High-speed RAM 512 bytes Buffer RAM 32 bytes Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) 1024 bytes 1024 bytesNote 2 instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 69 2 63 4 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS). 2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). 8 CHAPTER 1 GENERAL Table 1-2. Functional Outline of PD78054Y Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software PD78052Y PD78053Y PD78054Y PD78055Y PD78056Y PD78058Y PD78P058Y 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 6.0 V * 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) * 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)Note * 80-pin ceramic WQFN (14 x 14 mm)(PD78P058Y only) Note Under planning 9 CHAPTER 1 GENERAL Figure 1-3. Block Diagram of PD78064 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 P00 P01-P05 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 PORT1 TO1/P31 TI1/P33 8-bit TIMER/EVENT COUNTER 1 PORT2 TO2/P32 TI2/P34 P25-P27 8-bit TIMER/EVENT COUNTER 2 PORT3 P30-P37 PORT7 WATCHDOG TIMER PORT8 WATCH TIMER 78K/0 CPU CORE ROM PORT9 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE 0 P70-P72 P80-P87 P90-P97 PORT10 P100-P103 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF SERIAL INTERFACE 2 RAM PORT11 P110-P117 S0-S23 S24/P97S31/P90 LCD CONTROLLER/ DRIVER S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD A/D CONVERTER INTP0/P00INTP5/P05 INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL RESET X1 X2 XT1/P07 XT2 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC (VPP) Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): PD78P064 10 CHAPTER 1 GENERAL Table 1-3. Functional Outline of PD78064 Subseries Item Part Number Internal memory ROM PD78062 Mask ROM 16K bytes PD78063 PD78064 PD78P064 PROM 24K bytes 1024 bytes 32K bytes 32K bytesNote 1 1024 bytesNote 1 High-speed RAM 512 bytes LCD display RAM 40 x 4 bits Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Instruction set * Total : 57 I/O port (including pins multiplexed * CMOS input : 2 with segment signal output) * CMOS I/O : 55 A/D converter LCD controller/driver 8-bit resolution x 8 channels * Segment signal output : 40 max. * Common signal output : 4 max. * Bias : 1/2 or 1/3 bias selectable * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Serial interface Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 12, external: 6 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 6.0 V * * * * 100-pin 100-pin 100-pin 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) plastic LQFP (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) plastic QFP (14 x 20 mm) ceramic WQFN (14 x 20 mm)Note 2 (PD78P064 only) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS). 2. Under development 11 CHAPTER 1 GENERAL Figure 1-4. Block Diagram of PD78064Y Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 P00 P01-P05 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 PORT1 TO1/P31 TI1/P33 8-bit TIMER/EVENT COUNTER 1 PORT2 TO2/P32 TI2/P34 P25-P27 8-bit TIMER/EVENT COUNTER 2 PORT3 P30-P37 PORT7 WATCHDOG TIMER PORT8 WATCH TIMER 78K/0 CPU CORE ROM PORT9 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SDL/P27 SERIAL INTERFACE 0 P70-P72 P80-P87 P90-P97 PORT10 P100-P103 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF SERIAL INTERFACE 2 RAM PORT11 P110-P117 S0-S23 S24/P97S31/P90 LCD CONTROLLER/ DRIVER S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD A/D CONVERTER INTP0/P00INTP5/P05 INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL RESET X1 X2 XT1/P07 XT2 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC Remark The internal ROM and RAM capacities differ depending on the model. 12 CHAPTER 1 GENERAL Table 1-4. Functional Outline of PD78064Y Subseries Item Part Number Internal memory ROM PD78062Y Mask ROM 16K bytes PD78063Y PD78064Y 24K bytes 1024 bytes 32K bytes High-speed RAM 512 bytes LCD display RAM 40 x 4 bits Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Instruction set I/O port * Total : 57 (including pins multiplexed * CMOS input : 2 with segment signal output) * CMOS I/O : 55 A/D converter LCD controller/driver 8-bit resolution x 8 channels * Segment signal output : 40 max. * Common signal output : 4 max. * Bias : 1/2 or 1/3 bias selectable * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Serial interface Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 12, external: 6 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 6.0 V * 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) * 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) * 100-pin plastic QFP (14 x 20 mm) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software 13 CHAPTER 1 GENERAL Figure 1-5. Block Diagram of PD78078 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 P00 P01-P06 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 8-bit TIMER/EVENT COUNTER 2 PORT3 8-bit TIMER/EVENT COUNTER 5 P20-P27 P30-P37 TI5/TO5/P100 PORT4 P40-P47 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE ROM PORT5 P50-P57 PORT6 WATCHDOG TIMER P60-P67 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 PORT7 P70-P72 SERIAL INTERFACE 0 PORT8 P80-P87 PORT9 RAM PORT10 P90-P96 SERIAL INTERFACE 1 P100-P103 PORT12 SERIAL INTERFACE 2 P120-P127 PORT13 REAL-TIME OUTPUT PORT P130, P131 RTP0/P120RTP7/P127 AD0/P40AD7/P47 A0/P80A7/P87 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 A/D CONVERTER D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM capacitiy differs depending on the model. 2. ( ): PD78P078 14 CHAPTER 1 GENERAL Table 1-5. Functional Outline of PD78078 Subseries Item Part Number Internal memory ROM PD78076 Mask ROM 48K bytes 60K bytes PD78078 PROM PD78P078 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) timon clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 88 2 78 8 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel Timer * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Internal: 15, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V * * * * 100-pin 100-pin 100-pin 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) plastic LQFP (fine pitch) (14 x 14 mm, resin thickness 1.4 mm)Note 2 plastic QFP (14 x 20 mm, resin thickness 2.7 mm) ceramic WQFN (14 x 20 mm) (PD78P078 only) Vectored interrupt source Test input Maskable Non-maskable Software Supply voltage Package Notes 1. The internal ROM capacity can be changed by using a memory size select register (IMS). 2. Under planning 15 CHAPTER 1 GENERAL Figure 1-6. Block Diagram of PD78078Y Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 8-bit TIMER/EVENT COUNTER 2 PORT3 8-bit TIMER/EVENT COUNTER 5 P20-P27 P30-P37 TI5/TO5/P100 PORT4 P40-P47 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE ROM PORT5 P50-P57 PORT6 WATCHDOG TIMER P60-P67 WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 PORT7 P70-P72 SERIAL INTERFACE 0 PORT8 P80-P87 PORT9 RAM PORT10 P90-P96 SERIAL INTERFACE 1 P100-P103 PORT12 SERIAL INTERFACE 2 P120-P127 PORT13 REAL-TIME OUTPUT PORT P130, P131 RTP0/P120RTP7/P127 AD0/P40AD7/P47 A0/P80A7/P87 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 A/D CONVERTER D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM capacity differs depending on the model. 2. ( ): PD78P078Y 16 CHAPTER 1 GENERAL Table 1-6. Functional Outline of PD78078Y Subseries Item Part Number Internal memory ROM PD78076Y Mask ROM 48K bytes PD78078Y PROM 60K bytes PD78P078Y 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 88 2 78 8 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 15, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V * 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm) * 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness 1.4 mm)Note 2 * 100-pin ceramic WQFN (14 x 20 mm) (PD78P078Y only) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software Notes 1. The internal ROM capacity can be changed by using a memory size select register (IMS). 2. Under development 17 CHAPTER 1 GENERAL Figure 1-7. Block Diagram of PD78083 Subseries 8-bit TIMER/ EVENT COUNTER 5 P00 PORT0 P01-P03 TI5/TO5/P100 TI6/TO6/P101 5-bit TIMER/ EVENT COUNTER 6 78K/0 CPU CORE ROM PORT1 P10-P17 WATCHDOG TIMER SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF1 INTP1/P01INTP3/P03 PORT3 SERIAL INTERFACE 2 PORT5 A/D CONVERTER RAM INTERRUPT CONTROL PORT10 PORT7 P30-P37 P50-P57 P70-P72 P100, P101 BUZ/P36 BUZZER OUTPUT RESET X1 X2 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC (VPP) SYSTEM CONTROL Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): PD78P083 18 CHAPTER 1 GENERAL Table 1-7. Functional Outline of PD78083 Subseries Item Part Number Internal memory ROM PD78081 Mask ROM 8K bytes 16K bytes 384 bytes PD78082 PROM PD78P083 24K bytesNote 1 512 bytesNote 1 High-speed RAM 256 bytes Memory space General-purpose register Minimum instruction execution time Instruction set 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (with main system clock of 5.0 MHz) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. I/O port * Total : 33 * CMOS input : 1 * CMOS I/O : 32 8-bit resolution x 8 channels 3-wire serial I/O/UART mode selectable: 1 channel * 8-bit timer/event counter : 2 channels * Watchdog timer : 1 channel 2 (8-bit PWM output) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 8, external: 3 Internal: 1 1 VDD = 1.8 to 5.5 VNote 2 * 42-pin plastic shrink DIP (600 mil) * 42-pin ceramic shrink DIP (with window) (600 mil) (PD78P083 only) * 44-pin plastic QFP (10 x 10 mm) A/D converter Serial interface Timer Timer output Clock output Buzzer output Vectored interrupt source Maskable Non-maskable Software Supply voltage Package Notes 1. The capacities of the internal PROM and internal-high-speed RAM can be changed by using a memory size select register. (IMS) 2. The supply voltage (VDD) of the PD78081(A2) is 4.5 to 5.5 V. 19 CHAPTER 1 GENERAL Figure 1-8. Block Diagram of PD78098 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 P00 P01-P06 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT3 WATCHDOG TIMER PORT4 WATCH TIMER PORT5 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF1 ANO0/P130, ANO1/P131 AVSS AVREF0 INTP0/P00INTP6/P06 SERIAL INTERFACE 0 P20-P27 P30-P37 P40-P47 P50-P57 78K/0 CPU CORE ROM PORT6 P60-P67 PORT7 SERIAL INTERFACE 1 PORT12 P70-P72 P120-P127 SERIAL INTERFACE 2 RAM PORT13 REAL-TIME OUTPUT PORT IEBus CONTROLLER P130, P131 RTP0/P120RTP7/P127 TX/P124/RTP4 RX/P125/RTP5 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 A/D CONVERTER D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): PD78P098A 20 CHAPTER 1 GENERAL Table 1-8. Functional Outline of PD78098 Subseries (1/2) Item Part Number Internal memory ROM PD78094 Mask ROM 32K bytes PD78095 PD78096 PD78098ANote 1 PD78P098ANote 1, 2 PROM 40K bytes 48K bytes 60K bytes 60K bytesNote 3 High-speed RAM 1024 bytes Buffer RAM 32 bytes 2048 bytes 2048 bytesNote 4 Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.5 s/1.0 s/2.0 s/4.0 s/8.0 s/16.0 (at 6.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total : CMOS input : CMOS I/O : N-ch open-drain I/O: 69 2 63 4 Instruction set I/O port IEBus controller A/D converter D/A converter Serial interface Effective transfer rate: 3.9 kbps/17 kbps/26 kbps 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel Timer * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer output Clock output 3 (14-bit PWM output: 1) 15.6 kHz, 31.3 kHz, 62.5 kHz, 125 kHz, 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz, 4.0 MHz (with main system clock of 6.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. Under development 2. The PD78P098A is the PROM model of the PD78094, 78095, 78096, and 78098A. 3. The internal PROM capacity can be changed by using a memory size select register (IMS). 4. The internal expansion RAM can be changed by using an internal expansion RAM size select register (IXS). 21 CHAPTER 1 GENERAL Table 1-8. Functional Outline of PD78098 Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software PD78094 PD78095 PD78096 PD78098ANote 1 PD78P098ANote 1, 2 977 Hz, 1.95 kHz, 3.9 kHz, 7.8 kHz (with main system clock of 6.0 MHz) Internal: 14, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.7 to 6.0 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin ceramic WQFN (14 x 14 mm)Note 1 (PD78P098A only) Notes 1. Under development 2. The PD78P098A is a PROM model of the PD78094, 78095, 78096, and 78098A. 22 CHAPTER 1 GENERAL Figure 1-9. Block Diagram of PD780018 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit TIMER/ EVENT COUNTER P00 P01-P06 PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 P10-P17 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 PORT3 P30-P37 PORT4 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE ROM PORT5 P40-P47 P50-P57 WATCHDOG TIMER WATCH TIMER SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI4A/P90 SO4A/P91 SCK4A/P92 SI4B/P93 SO4B/P94 SCK4B/P95 SI4C/P110 SO4C/P111 SCK4C/P112 ANI0/P10ANI7/P17 AVSS AVREF INTP0/P00INTP6/P06 PORT6 P60-P67 PORT8 SERIAL INTERFACE 1 PORT9 RAM PORT10 P80-P87 P90-P96 P100-P103 SERIAL INTERFACE 4 PORT11 P110-P117 PORT15 P150-P156 A/D CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL AD0/P40AD7/P47 A0/P80A7/P87 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1 XT2 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, IC VDD1 VSS1 (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM capacity differs depending on the model. 2. ( ): PD78P0018 23 CHAPTER 1 GENERAL Table 1-9. Functional Outline of PD780018 Subseries (1/2) Item Part Number Internal memory ROM PD780016 Mask ROM 48K bytes PD780018 PROM 60K bytes PD78P0018 60K bytesNote High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. : 88 :9 : 79 Instruction set I/O port * Total * CMOS input * CMOS I/O A/D converter Serial interface 8-bit resolution x 8 channels * 3-wire serial I/O mode (with automatical transfer/reception function) * 3-wire serial I/O mode selectable (with time-division transfer function) * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel : 1 channel : 1 channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Note The internal ROM capacity can be changed by using a memory size select register. (IMS) Caution The PD780018 subseries is under planning. 24 CHAPTER 1 GENERAL Table 1-9. Functional Outline of PD780018 Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Operating temperature Package Maskable Non-maskable Software PD780016 PD780018 PD78P0018 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 12, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.7 to 5.5 V TA = -40 to +85 C * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (14 x 20 mm) (PD78P0018 only) Caution The PD780018 subseries is under planning. 25 CHAPTER 1 GENERAL Figure 1-10. Block Diagram of PD780018Y Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 P00 P01-P06 16-bit TIMER/ EVENT COUNTER PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 P10-P17 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 PORT3 P30-P37 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE ROM PORT4 P40-P47 WATCHDOG TIMER PORT5 P50-P57 WATCH TIMER PORT6 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI4A/P90 SO4A/P91 SCK4A/P92 SI4B/P93 SO4B/P94 SCK4B/P95 SI4C/P110 SO4C/P111 SCK4C/P112 PORT15 SDA/P116 SCL/P117 ANI0/P10ANI7/P17 AVSS AVREF INTP0/P00INTP6/P06 SERIAL INTERFACE 5 P150-P156 SERIAL INTERFACE 4 PORT11 P110-P117 P60-P67 SERIAL INTERFACE 1 RAM PORT8 P80-P87 PORT9 P90-P96 PORT10 P100-P103 A/D CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL AD0/P40AD7/P47 A0/P80A7/P87 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1 XT2 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, IC VDD1 VSS1 (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM capacity differs depending on the model. 2. ( ): PD78P0018Y 26 CHAPTER 1 GENERAL Table 1-10. Functional Outline of PD780018Y Subseries (1/2) Item Part Number Internal memory ROM PD780016Y Mask ROM 48K bytes PD780018Y PROM 60K bytes PD78P018Y 60K bytesNote High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. : 88 :9 : 79 Instruction set I/O port * Total * CMOS input * CMOS I/O A/D converter Serial interface 8-bit resolution x 8 channels * * * * * * * 3-wire serial I/O mode (with automatical transfer/reception function) 3-wire serial I/O mode selectable (with time-division transfer function) I2C bus mode (multi-master compatible) 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel : 1 channel : 1 channel : 1 channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Note The internal PROM capacity can be changed by using a memory size select register. (IMS) Caution The PD780018Y subseries is under development. 27 CHAPTER 1 GENERAL Table 1-10. Functional Outline of PD78P0018Y Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Operating temperature Package Maskable Non-maskable Software PD780016Y PD780018Y PD78P018Y 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 12, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.7 to 5.5 V TA = -40 to +85 C * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (14 x 20 mm) (PD78P0018Y only) Caution The PD780018Y subseries is under development. 28 CHAPTER 1 GENERAL Figure 1-11. Block Diagram of PD780058 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P05 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 WATCHDOG TIMER PORT3 P30-P37 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/TxD1/P23 BUSY/RxD1/P24 BUSY/RxD1/P24 STB/TxD1/P23 SI2/RxD0/P70 SO2/TxD0/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP5/P05 PORT4 P40-P47 SERIAL INTERFACE 0 78K/0 CPU CORE ROM FLASH MEMORY PORT5 P50-P57 PORT6 SERIAL INTERFACE 1 PORT7 P60-P67 P70-P72 SERIAL INTERFACE 2 PORT12 RAM PORT13 P120-P127 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, IC VDD1 VSS1 (VPP) PCL/P35 CLOCK OUTPUT CONTROL RESET X1 X2 XT1/P07 XT2 Remarks 1. The capacities of the internal ROM and RAM differ depending on the model. 2. ( ): PD78F0058 29 CHAPTER 1 GENERAL Table 1-11. Functional Outline of PD780058 Subseries (1/2) Item Part Number Internal memory ROM PD780053 Mask ROM 24K bytes PD780054 PD780055 PD780056 PD780058 PD78F0058 Flash memory 32K bytes 40K bytes 48K bytes 60K bytes 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes 1024 bytes 1024 bytesNote 2 Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 68 2 62 4 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable (with time-division transfer function) : 1 channel Timer * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The capacities of the flash memory can be changed by using a memory size select register (IMS). 2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). Caution The PD780058 subseries is under development. 30 CHAPTER 1 GENERAL Table 1-11. Functional Outline of PD780058 Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Operating temperature Package Maskable Non-maskable Software PD780053 PD780054 PD780055 PD780056 PD780058 PD78F0058 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V TA = -40 to +85 C * 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) * 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)Note * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) Note Under planning Caution The PD780058 subseries is under development. 31 CHAPTER 1 GENERAL Figure 1-12. Block Diagram of PD780058Y Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P05 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 WATCHDOG TIMER PORT3 P30-P37 WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/TxD1/P23 BUSY/RxD1/P24 BUSY/RxD1/P24 STB/TxD1/P23 SI2/RxD0/P70 SO2/TxD0/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP5/P05 PORT4 P40-P47 SERIAL INTERFACE 0 78K/0 CPU CORE ROM FLASH MEMORY PORT5 P50-P57 PORT6 SERIAL INTERFACE 1 PORT7 P60-P67 P70-P72 SERIAL INTERFACE 2 PORT12 RAM PORT13 P120-P127 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, IC VDD1 VSS1 (VPP) PCL/P35 CLOCK OUTPUT CONTROL RESET X1 X2 XT1/P07 XT2 Remarks 1. The capacities of the internal ROM and RAM differ depending on the model. 2. ( ): PD78F0058Y 32 CHAPTER 1 GENERAL Table 1-12. Functional Outline of PD780058Y Subseries (1/2) Item Part Number Internal memory ROM PD780053Y Mask ROM 24K bytes PD780054Y PD780055Y PD780056Y PD780058Y PD78F0058Y Flash memory 32K bytes 40K bytes 48K bytes 60K bytes 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes 1024 bytes 1024 bytesNote 2 Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 68 2 62 4 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable (with time-division transfer function) : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The capacities of the flash memory can be changed by using a memory size select register (IMS). 2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). Caution The PD780058Y subseries is under planning. 33 CHAPTER 1 GENERAL Table 1-12. Functional Outline of PD780058Y Subseries (2/2) Item Part Number Buzzer output Vectored interrupt Maskable Non-maskable Software Test input Supply voltage Operating temperature Package PD780053Y PD780054Y PD780055Y PD780056Y PD780058Y PD78F0058Y 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V TA = -40 to +85 C * 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) * 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) Caution The PD780058Y subseries is under planning. 34 CHAPTER 1 GENERAL Figure 1-13. Block Diagram of PD780308 Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P05 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT3 WATCHDOG TIMER PORT7 WATCH TIMER PORT8 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI2/RXD/P70 SO2/TXD/P71 RXD/P114 TXD/P113 SCK2/ASCK/P72 SI3/P110 SO3/P111 SCK3/P112 ANI0/P10ANI7/P17 AVDD AVSS AVREF SERIAL INTERFACE 0 78K/0 CPU CORE ROM PORT9 P25-P27 P30-P37 P70-P72 P80-P87 P90-P97 SERIAL INTERFACE 2 PORT10 P100-P103 PORT11 SERIAL INTERFACE 3 RAM P110-P117 S0-S23 S24/P97S31/P90 A/D CONVERTER LCD CONTROLLER/ DRIVER S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD RESET X1 X2 XT1/P07 XT2 INTP0/P00INTP5/P05 INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, IC VDD1, VSS1, (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM capacity differs depending on the model. 2. ( ): PD78P0308 35 CHAPTER 1 GENERAL Table 1-13. Functional Outline of PD780308 Subseries Item Part Number Internal memory ROM PD780306 Mask ROM 48K bytes PD780308 PROM 60K bytes PD78P0308 60K bytesNote High-speed RAM 1024 bytes Expansion RAM 1024 bytes LCD display RAM 40 x 4 bits Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Instruction set * Total : 57 I/O port (including pins multiplexed * CMOS input : 2 with segment signal output) * CMOS I/O : 55 A/D converter LCD controller/driver 8-bit resolution x 8 channels * Segment signal output : 40 max. * Common signal output : 4 max. * Bias : 1/2 or 1/3 bias selectable * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable * 3-wire serial I/O/UART mode selectable * 3-wire serial I/O mode * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel : 1 channel : 1 channel : 1 channel Serial interface Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 6 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 5.5 V * 100-pin plastic QFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (14 x 20 mm) (PD78P0308 only) Buzzer output Vectored interrupt Maskable Non-maskable Software Test input Supply voltage Package Note The capacity of the internal PROM can be changed by using a memory size select register (IMS). Caution The PD780308 subseries is under development. 36 CHAPTER 1 GENERAL Figure 1-14. Block Diagram of PD780308Y Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P05 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT3 WATCHDOG TIMER PORT7 WATCH TIMER PORT8 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 RxD/P114 TxD/P113 SCK0/SDL/P27 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 SI3/P110 SO3/P111 SCK3/P112 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 78K/0 CPU CORE SERIAL INTERFACE 0 ROM PORT9 P25-P27 P30-P37 P70-P72 P80-P87 P90-P97 PORT10 SERIAL INTERFACE 2 P100-P103 PORT11 RAM P110-P117 SERIAL INTERFACE 3 S0-S23 S24/P97S31/P90 A/D CONVERTER LCD CONTROLLER/ DRIVER S32/P87S39/P80 COM0-COM3 VLC0-VLC2 INTERRUPT CONTROL BIAS fLCD BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL PCL/P35 CLOCK OUTPUT CONTROL VDD0, VSS0, VDD1, VSS1, IC RESET X1 X2 XT1/P07 XT2 Remarks 1. The internal ROM capacity differs depending on the model. 2. ( ): PD78P0308Y 37 CHAPTER 1 GENERAL Table 1-14. Functional Outline of PD780308Y Subseries Item Part Number Internal memory ROM PD780306Y Mask ROM 48K bytes PD780308Y PROM 60K bytes PD78P0308Y 60K bytesNote High-speed RAM 1024 bytes Expansion RAM 1024 bytes LCD display RAM 40 x 4 bits Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) Instruction system clock execution With subsystem 122 s (at 32.768 kHz) cycle clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Instruction set * Total : 57 I/O port * CMOS input : 2 (including pins multiplexed with segment signal output) * CMOS I/O : 55 A/D converter LCD controller/driver 8-bit resolution x 8 channels * Segment signal output : 40 max. * Common signal output : 4 max. * Bias : 1/2 or 1/3 bias selectable * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable * 3-wire serial I/O/UART mode selectable * 3-wire serial I/O mode * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel : 1 channel : 1 channel : 1 channel Serial interface Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 6 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 5.5 V * 100-pin plastic QFP (14 x 20 mm) * 100-pin ceramic WQFN (14 x 20 mm) (PD78P0308Y only) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software Note The capacity of the internal PROM can be changed by using a memory size select register (IMS). Caution The PD780308Y subseries is under development. 38 CHAPTER 1 GENERAL Figure 1-15. Block Diagram of PD78058F Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT3 WATCHDOG TIMER PORT4 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVREF0 ANO0/P130, ANO1/P131 AVREF1 EXTERNAL ACCESS INTP0/P00INTP6/P06 INTERRUPT CONTROL PORT5 SERIAL INTERFACE 0 78K/0 CPU CORE ROM PORT6 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 SERIAL INTERFACE 1 PORT7 P70-P72 PORT12 SERIAL INTERFACE 2 P120-P127 RAM PORT13 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 D/A CONVERTER BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS AVDD AVSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): PD78P058F 39 CHAPTER 1 GENERAL Table 1-15. Functional Outline of PD78058F Subseries (1/2) Item Part Number Internal memory ROM PD78056F Mask ROM 48K bytes PD78058F PROM 60K bytes PD78P058F 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes 1024 bytes 1024 bytesNote 2 Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 69 2 63 4 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The capacity of the internal PROM can be changed by using a memory size select register (IMS). 2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). 40 CHAPTER 1 GENERAL Table 1-15. Functional Outline of PD78058F Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software PD78056F PD78058F PD78P058F 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Internal: 1 Internal: 1 Internal: 1, external: 1 VDD = 2.7 to 6.0 V * 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) * 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)Note * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) (PD78058F only) Note Under planning 41 CHAPTER 1 GENERAL Figure 1-16. Block Diagram of PD78058FY Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT3 WATCHDOG TIMER PORT4 WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVREF0 ANO0/P130, ANO1/P131 AVREF1 EXTERNAL ACCESS INTP0/P00INTP6/P06 INTERRUPT CONTROL PORT5 SERIAL INTERFACE 0 78K/0 CPU CORE ROM PORT6 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 SERIAL INTERFACE 1 PORT7 P70-P72 PORT12 SERIAL INTERFACE 2 P120-P127 RAM PORT13 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 D/A CONVERTER BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS AVDD AVSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The capacities of the internal ROM and RAM differ depending on the model. 2. ( ): PD78P058FY 42 CHAPTER 1 GENERAL Table 1-16. Functional Outline of PD78058FY Subseries (1/2) Item Part Number Internal memory ROM PD78056FY Mask ROM 48K bytes PD78058FY PROM 60K bytes PD78P058FY 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes 1024 bytes 1024 bytesNote 2 Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 69 2 63 4 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The capacity of the internal PROM can be changed by using a memory size select register (IMS). 2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). 43 CHAPTER 1 GENERAL Table 1-16. Functional Outline of PD78058FY Subseries (2/2) Item Part Number Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software PD78056FY PD78058FY PD78P058FY 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 13, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.7 to 6.0 V * 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) * 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)Note * 80-pin plastic TQFP (fine pitch)(12 x 12 mm) (PD78058FY only) Note Under planning 44 CHAPTER 1 GENERAL Figure 1-17. Block Diagram of PD78064B Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P05 P07 P10-P17 PORT1 TO1/P31 TI1/P33 8-bit TIMER/EVENT COUNTER 1 PORT2 P25-P27 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT3 P30-P37 PORT7 WATCHDOG TIMER PORT8 WATCH TIMER 78K/0 CPU CORE ROM PORT9 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 P70-P72 P80-P87 P90-P97 SERIAL INTERFACE 0 PORT10 P100-P103 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 PORT11 SERIAL INTERFACE 2 RAM P110-P117 S0-S23 S24/P97S31/P90 ANI0/P10ANI7/P17 AVREF A/D CONVERTER LCD CONTROLLER/ DRIVER INTERRUPT CONTROL S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD INTP0/P00INTP5/P05 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL RESET X1 X2 XT1/P07 XT2 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS AVDD AVSS IC (VPP) Remark ( ): PD78P064B 45 CHAPTER 1 GENERAL Table 1-17. Functional Outline of PD78064B Subseries Item Part Number Internal memory ROM Mask ROM 32K bytes High-speed RAM 1024 bytes LCD display RAM 40 x 4 bits Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) PD78064B PROM PD78P064B instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Instruction set * Total : 57 I/O port (including pins multiplexed * CMOS input : 2 with segment signal output) * CMOS I/O : 55 A/D converter LCD controller/driver 8-bit resolution x 8 channels * Segment signal output : 40 max. * Common signal output : 4 max. * Bias : 1/2 or 1/3 bias selectable * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable * 3-wire serial I/O/UART mode selectable * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel : 1 channel : 1 channel Serial interface Timer Timer output Clock output 3 (14-bit PWM output: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 12, external: 6 Internal: 1 1 Internal: 1, external: 1 VDD = 2.0 to 6.0 V * 100-pin plastic QFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software 46 CHAPTER 1 GENERAL Figure 1-18. Block Diagram of PD78070A TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 8-bit TIMER/EVENT COUNTER 1 PORT1 P10-P17 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 PORT3 P30-P37 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE RAM PORT6 P60-P63,P66 WATCHDOG TIMER PORT7 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 PORT9 P70-P72 SERIAL INTERFACE 0 P90-P96 PORT10 SERIAL INTERFACE 1 PORT12 P100-P103 P120-P127 SERIAL INTERFACE 2 PORT13 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0-AD7 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL A0-A15 RD WR WAIT/P66 RESET X1 X2 XT1/P07 XT2 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC PCL/P35 CLOCK OUTPUT CONTROL 47 CHAPTER 1 GENERAL Table 1-18. Functional Outline of PD78070A Part Number Internal memory ROM None Functions High-speed RAM 1024 bytes Buffer RAM 32 bytes 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) Memory space General-purpose register Minimum With main instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 61 2 51 8 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serail I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Internal: 15, external: 7 Internal: 1 1 Internal: 1 VDD = 2.7 to 5.5 V * 100-pin plastic QFP (fine pitch) (14 x 14 mm) * 100-pin plastic QFP (14 x 20 mm) Vectored interrupt source Test input Maskable Non-maskable Software Supply voltage Package 48 CHAPTER 1 GENERAL Figure 1-19. Block Diagram of PD78070AY TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 8-bit TIMER/EVENT COUNTER 1 PORT1 P10-P17 8-bit TIMER/EVENT COUNTER 2 PORT2 P20-P27 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 PORT3 P30-P37 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE RAM PORT6 P60-P63, P66 WATCHDOG TIMER PORT7 WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 PORT9 P70-P72 SERIAL INTERFACE 0 P90-P96 PORT10 SERIAL INTERFACE 1 PORT12 P100-P103 P120-P127 SERIAL INTERFACE 2 PORT13 P130, P131 A/D CONVERTER REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 AD0-AD7 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL A0-A15 RD WR WAIT/P66 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS IC PCL/P35 CLOCK OUTPUT CONTROL RESET X1 X2 XT1/P07 XT2 49 CHAPTER 1 GENERAL Table 1-19. Functional Outline of PD78070AY Part Number Internal memory ROM None Functions High-speed RAM 1024 bytes Buffer RAM 32 bytes 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) Memory space General-purpose register Minimum With main instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 61 2 51 8 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 15, external: 7 Internal: 1 1 Internal: 1 VDD = 2.7 to 5.5 V * 100-pin plastic QFP (14 x 20 mm) * 100-pin plastic QFP (fine pitch) (14 x 14 mm) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software 50 CHAPTER 1 GENERAL Figure 1-20. Block Diagram of PD78075B Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 P00 P01-P06 P07 P10-P17 16-bit TIMER/ EVENT COUNTER PORT0 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 8-bit TIMER/EVENT COUNTER 2 P20-P27 PORT3 P30-P37 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 PORT4 P40-P47 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE ROM PORT5 P50-P57 PORT6 P60-P67 WATCHDOG TIMER PORT7 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 PORT8 SERIAL INTERFACE 0 PORT9 RAM SERIAL INTERFACE 1 PORT10 P70-P72 P80-P87 P90-P96 P100-P103 PORT12 SERIAL INTERFACE 2 P120-P127 PORT13 REAL-TIME OUTPUT PORT P130, P131 RTP0/P120RTP7/P127 AD0/P40AD7/P47 A0/P80A7/P87 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 A/D CONVERTER D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, VDD1 VSS1 IC PCL/P35 CLOCK OUTPUT CONTROL Remark The internal ROM capacity differs depending on the model. 51 CHAPTER 1 GENERAL Table 1-20. Functional Outline of PD78075B8 Subseries Item Part Number Internal memory ROM Mask ROM 40K bytes PD78074B PD78075B High-speed RAM 32K bytes Buffer RAM 1024 bytes Expansion RAM 32 bytes Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 88 2 78 8 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Internal: 15, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V * 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) * 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm) Vectored interrupt source Test input Maskable Non-maskable Software Supply voltage Package 52 CHAPTER 1 GENERAL Figure 1-21. Block Diagram of PD78075BY Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 8-bit TIMER/EVENT COUNTER 2 P20-P27 PORT3 P30-P37 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 PORT4 P40-P47 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 78K/0 CPU CORE ROM PORT5 P50-P57 PORT6 P60-P67 WATCHDOG TIMER PORT7 WATCH TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVSS AVREF0 ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 PORT8 SERIAL INTERFACE 0 PORT9 RAM SERIAL INTERFACE 1 PORT10 P70-P72 P80-P87 P90-P96 P100-P103 PORT12 P120-P127 SERIAL INTERFACE 2 PORT13 REAL-TIME OUTPUT PORT P130, P131 RTP0/P120RTP7/P127 AD0/P40AD7/P47 A0/P80A7/P87 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 A/D CONVERTER D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD0, VSS0, IC VDD1 VSS1 (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remark The internal ROM capacity differs depending on the model. 53 CHAPTER 1 GENERAL Table 1-21. Functional Outline of PD78075BY Subseries Item Part Number Internal memory ROM Mask ROM 32K bytes High-speed RAM 1024 bytes Buffer RAM Memory space General-purpose register Minimum With main 32 bytes 64K bytes 8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz) 40K bytes PD78074BY PD78075BY instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total CMOS input CMOS I/O N-ch open-drain I/O : : : : 88 2 78 8 Instruction set I/O port A/D converter D/A converter Serial interface 8-bit resolution x 8 channels 8-bit resolution x 2 channels : 1 channel * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Timer Timer output Clock output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Internal: 15, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 1.8 to 5.5 V * 100-pin plastic QFP (14 x 20 mm, resin thickness 2.7 mm) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software Caution The PD78075BY subseries is under development. 54 CHAPTER 1 GENERAL Figure 1-22. Block Diagram of PD78098B Subseries TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER PORT0 P00 P01-P06 P07 P10-P17 8-bit TIMER/EVENT COUNTER 1 PORT1 PORT2 TO2/P32 TI2/P34 8-bit TIMER/EVENT COUNTER 2 P20-P27 PORT3 P30-P37 WATCHDOG TIMER PORT4 P40-P47 WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVREF1 ANO0/P130, ANO1/P131 AVREF0 INTP0/P00INTP6/P06 PORT5 P50-P57 SERIAL INTERFACE 0 78K/0 CPU CORE ROM PORT6 P60-P67 PORT7 SERIAL INTERFACE 1 P70-P72 PORT12 P120-P127 PORT13 SERIAL INTERFACE 2 RAM REAL-TIME OUTPUT PORT IEBus CONTROLLER P130, P131 RTP0/P120RTP7/P127 TX/P124/RTP4 RX/P125/RTP5 AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P07 XT2 A/D CONVERTER D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL VDD VSS AVDD AVSS IC (VPP) PCL/P35 CLOCK OUTPUT CONTROL Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): PD78P098B 55 CHAPTER 1 GENERAL Table 1-22. Functional Outline of PD78098B Subseries Item Part Number Internal memory ROM PD78095B Mask ROM 40K bytes PD78096B PD78098B PD78P098B PROM 48K bytes 60K bytes 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes 2048 bytes 2048 bytesNote 2 Expansion RAM None Memory space General-purpose register Minimum With main 64K bytes 8 bits x 8 x 4 banks 0.5 s/1.0 s/2.0 s/4.0 s/8.0 s/16.0 (at 6.0 MHz) instruction system clock execution With subsystem 122 s (at 32.768 kHz) time clock * * * * * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Total : CMOS input : CMOS I/O : N-ch open-drain I/O: 69 2 63 4 3.9 kbps/17 kbps/26 kbps Instruction set I/O port IEBus controller A/D converter D/A converter Serial interface Effective transfer rate: 8-bit resolution x 8 channels 8-bit resolution x 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel * 3-wire serial I/O/UART mode selectable : 1 channel * * * * 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Timer Timer output Clock output 3 (14-bit PWM output: 1) 15.6 kHz, 31.3 kHz, 62.5 kHz, 125 kHz, 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz, 4.0 MHz (with main system clock of 6.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) 977 Hz, 1.95 kHz, 3.9 kHz, 7.8 kHz (with main system clock of 6.0 MHz) Internal: 14, external: 7 Internal: 1 1 Internal: 1, external: 1 VDD = 2.7 to 6.0 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin ceramic WQFN (14 x 14 mm) (PD78P098B only) Buzzer output Vectored interrupt source Test input Supply voltage Package Maskable Non-maskable Software Notes 1. The internal PROM capacity can be changed by using a memory size select register (IMS). 2. The internal expansion RAM can be changed by using an internal expansion RAM size select register (IXS). Caution The PD78098B subseries is under planning. 56 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.1 Data Transfer Data is exchanged by using an address specified by the DE and HL registers as the first address. The number of bytes of the data to be exchanged is specified by the B register. Figure 2-1. Data Exchange Address DE + B - 1 Address HL + B - 1 Data exchange DE HL (1) Registers used A, B, DE, HL (2) Program list EXCH: MOV XCH XCH INCW INCW DBNZ RET A,[DE] A,[HL] A,[DE] DE HL B,$EXCH 57 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.2 Data Comparison Data is compared by using an address specified by the DE and HL registers as the first address. The number of bytes of the data to be compared is specified by the B register. If the result of comparison is equal, CY is cleared to 0; if not, CY is set to 1. Figure 2-2. Data Comparison Address DE + B - 1 Address HL + B - 1 Data comparison DE HL (1) Registers used A, B, DE, HL (2) Program list COMP: MOV CMP BNZ INCW INCW DBNZ CLR1 BR ERROR: SET1 RTN: RET CY A,[DE] A,[HL] $ERROR DE HL B,$COMP CY RTN 58 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.3 Decimal Addition The lowest address for decimal addition is specified by the DE and HL registers, and the number of digits specified by BYTNUM is added. The result of the addition is stored to an area specified by the HL register. If an overflow or underflow occurs as a result of the addition, execution branches to error processing. Define the branch address as `ERROR' in the main routine. Also declare it as PUBLIC. Figure 2-3. Decimal Addition Address DE + BYTNUM - 1 Address HL + BYTNUM - 1 Address HL + BYTNUM - 1 + DE HL = HL (1) Flowchart BCDADD C number of bytes for decimal addition BC-1 Number of bytes for decimal addition without sign BCDAD2 Signs of augend and addend same? Yes Decimal addition processing No Decimal subtraction processing RET 59 CHAPTER 2 FUNDAMENTALS OF SOFTWARE DADDS CY 0 Sign flag SFLAG 0 DADDS1 A [DE] + [HL] + CY Adds augend and addend with CY Adjusts result to decimal and stores in memory DE DE + 1, HL HL + 1 Increments addend and augend addresses BB-1 No B=0 Yes A [DE] + [HL] + CY Adds addend and augend with CY CY = 1 Yes Sign flag SFLAG 1 CY = 0 DADDS3 Result adjusted to decimal? No CY = 1 No A7 = 1 No Yes Yes ERROR Sign flag SFLAG = 1 Yes A7 1 DADDS6 Stores A to memory RET No 60 CHAPTER 2 FUNDAMENTALS OF SOFTWARE DSUBS Makes subtrahend positive Sign flag SFLAG 0 Minuend < 0 Yes Makes subtrahend positive Sign flag SFLAG 1 DSUBS1 B C, CY 0 DSUBS2 A [DE] - [HL] - CY Subtracts subtrahend from minuend with CY DE DE + 1, HL HL + 1 Increments subtrahend and minuend addresses No Adjusts result to decimal and stores in memory CC-1 No C=0 Yes CY = 1 Yes Inverts sign flag that takes 10's complement DSUBS5 Result = 0 No Sign flag = 1 Yes Appends negative sign to result No Yes No RET 61 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (2) Registers used AX, BC, DE, HL (3) Program list ;****************************************************************** ; * ; Input parameter * ; HL register: addend first address * ; DE register: augend first address * ; Output parameter * ; HL register: Operation result first address * ; * ;****************************************************************** PUBLIC PUBLIC PUBLIC EXTRN EXTBIT ; BYTNUM EQU ; CSEG BCDADD: MOV BCDAD1: MOV MOV DEC BCDAD2: MOV XCHW XCHW XCHW XOR XCHW XCHW XCHW BT CALL RET BCDAD3: CALL RET !DSUBS BCDADD,BCDAD1,BCDAD2 DADDS DSUBS ERROR SFLAG 4 ; Error processing branch address ; Sign flag ; Sets number of digits for operation C,#BYTNUM A,C B,A B A,[HL+BYTNUM-1] AX,DE AX,HL AX,DE A,[HL+BYTNUM-1] AX,HL AX,DE AX,HL A.7,$BCDAD3 !DADDS ; Sets number of digits for operation to C register ; Loads MSB (sign data) of augend ; Loads MSB (sign data) of augend ; Signs coincide? ELSE subtraction processing ; THEN addition processing 62 CHAPTER 2 FUNDAMENTALS OF SOFTWARE ;============================================================= ; ***** 10 Decimal addition ***** ;============================================================= DADDS: CLR1 CLR1 DADDS1: MOV ADDC ADJBA MOV INCW INCW DBNZ MOV ADDC DADDS2: BNC SET1 CLR1 DADDS3: ADJBA BNC BR DADDS4: BF BR DADDS5: BF SET1 DADDS6: MOV RET [HL],A SFLAG,$DADDS6 A.7 ; Sets sign CY SFLAG A,[DE] A,[HL] [HL],A HL DE B,$DADDS1 A,[DE] A,[HL] $DADDS3 SFLAG CY ; Negative addition ; THEN sets negative status ; Starts addition from lowest digit ; End of addition (number of digits for operation - 1) $DADDS4 ERROR A.7,$DADDS5 ERROR 63 CHAPTER 2 FUNDAMENTALS OF SOFTWARE ;================================================================ ; ***** 10 Decimal subtraction ***** ;================================================================ DSUBS: PUSH CLR1 MOV CLR1 MOV XCHW XCHW XCHW MOV BF CLR1 MOV SET1 DSUBS1: XCHW XCHW XCHW MOV MOV CLR1 DSUBS2: MOV SUBC ADJBS MOV INCW INCW DBNZ BNC POP PUSH MOV MOV DSUBS3: MOV SUB ADJBS MOV INCW DBNZ A,#99H A,[HL] [HL],A HL C,$DSUBS3 ; Complement operation of result of subtraction ; (result of subtraction - 99H) HL SFLAG A,[HL+BYTNUM-1] A.7 [HL+BYTNUM-1],A AX,DE AX,HL AX,DE A,[HL+BYTNUM-1] A.7,$DSUBS1 A.7 [HL+BYTNUM-1],A SFLAG AX,HL AX,DE AX,HL A,C B,A CY A,[DE] A,[HL] [HL],A HL DE C,$DSUBS2 $DSUBS5 HL HL A,B C,A ; Sets subtrahend as positive value ; Minuend is negative ; THEN sets minuend as positive value ; Sets sign as negative ; End of subtraction of number of digits for operation ; THEN subtrahend > minuend POP PUSH SET1 MOV MOV DSUBS4: MOV ADDC ADJBA HL HL CY A,B C,A A,#0 A,[HL] ; Adds 1 to result of complement operation 64 CHAPTER 2 FUNDAMENTALS OF SOFTWARE MOV [HL],A INCW HL DBNZ C,$DSUBS4 MOV1 CY,SFLAG NOT1 CY MOV1 SFLAG,CY ;====================================================== ; ***** 0 check of operation result ***** ;====================================================== DSUBS5: MOV MOV POP PUSH MOV DSUBS6: CMP INCW BNZ DBNZ POP RET DSUBS7: BF POP PUSH MOV SET1 MOV DSUBS8: POP RET HL SFLAG,$DSUBS8 HL HL A,[HL+BYTNUM-1] A.7 [HL+BYTNUM-1],A ; Result of subtraction is negative ; THEN sets sign A,B C,A HL HL A,#0 A,[HL] HL $DSUBS7 C,$DSUBS6 HL ; 0 check from lowest digit ; 0 check of all digits completed ; THEN result of subtraction = 0 65 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.4 Decimal Subtraction The lowest address for decimal subtraction is specified by the DE and HL registers, and the number of digits specified by BYTNUM is subtracted. The result of the subtraction is stored to an area specified by the HL register. If an overflow or underflow occurs as a result of the subtraction, execution branches to error processing. Define the branch address as `ERROR' in the main routine. Also declare it as PUBLIC. This program replaces minuend and subtrahend with augend and addend, and calls a program of decimal addition. Figure 2-4. Decimal Subtraction Address DE + BYTNUM - 1 Address HL + BYTNUM - 1 Address HL + BYTNUM - 1 - DE HL = HL (1) Flowchart BCDSUB C number of bytes for decimal subtraction Inverts sign bit of subtrahend Decimal addition with subtrahend and minuend as addend and augend RET (2) Registers used AX, BC, DE, HL 66 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (3) Program list ;****************************************************************** ; * ; Input parameter * ; HL register: subtrahend first address * ; DE register: minuend first address * ; Output parameter * ; HL register: Operation result first address * ; * ;****************************************************************** PUBLIC BYTNUM PUBLIC BCDSUB EXTRN BCDADD,BCDAD2 ; BYTNUM EQU ; CSEG BCDSUB: MOV BCDSU1: MOV MOV DEC MOV MOV1 NOT1 MOV1 MOV CALL RET 4 ; Sets number of digits for operation C,#BYTNUM A,C B,A B A,[HL+BYTNUM-1] CY,A.7 CY A.7,CY [HL+BYTNUM-1],A !BCDAD2 ; Sets number of digits for operation to C register ; Sets MSB (sign data) of subtrahend for addition ; Inverts sign data ; Calls decimal addition processing 67 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.5 Binary-to-Decimal Conversion Binary data of 16 bits in data memory is converted into 5-digit decimal data and stored in data memory. Binary data of 16 bits is divided by decimal 10 by the number of times equal to the number of digits (4 times), and conversion is carried out with the result of the operation and the value of the remainder at that time. Figure 2-5. Binary-to-Decimal Conversion Low x x x High x Low 0 x 0 x 0 x 0 x 0 High x Binary 16 bits (2 bytes) Decimal 5 digits (5 bytes) Example To convert FFH into decimal number Low F F 0 High 0 Low 0 5 0 5 0 2 0 0 0 High 0 Binary 16 bits (2 bytes) Decimal 5 digits (5 bytes) (1) Registers used AX, BC, HL 68 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (2) Program list PUBLIC B_DCONV DATDEC EQU 10 DSEG DS DS SADDRP 2 5 4 REGA: REGB: ; Stores binary 16-bit data ; Stores decimal 5-digit data COLNUM EQU B_DCONV: MOVW MOV MOVW B_D1: MOV DIVUW XCH MOV INCW XCH DBNZ MOV MOV RET AX,REGA B,#COLNUM HL,#REGB C,#DATDEC C A,C [HL],A HL A,C B,$B_D1 A,X [HL],A 69 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.6 Bit Manipulation Instruction A 1 bit of a flag in the data memory is ANDed with the bit 4 of port 6, and the result is ANDed with the bit 5 of port 6 and is output to the bit 6 of port 6. Figure 2-6. Bit Operation FLG PORT6.4 PORT6.5 PORT6.6 (1) Program list PUBLIC BIT_OP,FLG BSEG FLG BIT_OP: MOV1 AND1 OR1 MOV1 RET CY,FLG CY,P6.4 CY,P6.5 P6.6,CY DBIT 70 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.7 Binary Multiplication (16 bits x 16 bits) Data in a multiplicand area (HIKAKE; 16 bits) and multiplier area (KAKE; 16 bits) are multiplied, and the result is stored in an operation result storage area (KOTAE). Figure 2-7. Binary Multiplication HIKAKE + 1 Multiplicand area (2 bytes) HIKAKE x KAKE + 1 Multiplier area (2 bytes) KAKE KOTAE + 3 Operation result storage area (4 bytes) = KOTAE 71 CHAPTER 2 FUNDAMENTALS OF SOFTWARE EXTRN EXTRN MAIN: * * HIKAKE=WORKA (A) HIKAKE+1=WORKA+1 (A) KAKE=WORKB (A) KAKE+1=WORKB+1 (A) CALL !S_KAKERU HL=#KOTAE * * * S_KAKERU HIKAKE,KAKE,KOTAE ; Multiplier ; ; ; ; ; ; ; Stores multiplicand data to multiplicand area Stores multiplier data to multiplier area Calls multiplication routine HL RAM address of operation result storage area Stores result by indirect address transfer Caution Manipulate the data memory in 8-bit units. 72 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (1) Input/output condition * Input parameter HIKAKE : Store the multiplicand data in this area. KAKE : Store the multiplier data in this area. * Output parameter KOTAE : Store the result of the operation in this area. (2) SPD chart [Multiplication subroutine] S_KAKERU Initializes operation result storage area WORK1 multiplier (low) for (B = #0 ; B < #16 ; B + +) if (B = #8) THEN WORK1 multiplier (high) Shifts WORK1 1 bit to left if_bit (CY = #1) THEN Adds multiplicand to operation result storage area if (B #15) THEN Shifts operation result storage area 1 bit to left (3) Registers used A, B 73 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (4) Program list $PC(054) ; PUBLIC HIKAKE,S_KAKERU,KAKE,KOTAE ; ;************************************************ ; RAM definition ;************************************************ DSEG SADDR ; HIKAKE: DS 2 ; KAKE: DS 2 ; WORK1: DS 1 ; KOTAE: DS 4 ; ;************************************************ ; Multiplication ;************************************************ ; CSEG ; S_KAKERU: ; WORK1=KAKE+1 (A) ; KOTAE=#0 ; KOTAE+1=#0 ; KOTAE+2=#0 ; KOTAE+3=#0 ; for(B=#0;B<#16;B++)(A) ; if(B == #8)(A) ; WORK1=KAKE (A) ; endif ; A=WORK1 ; CLR1 CY ; ROLC A,1 ; WORK1=A ; if_bit(CY) ; KOTAE+=HIKAKE (A) ; (KOTAE+1)+=HIKAKE+1,CY (A) ; (KOTAE+2)+=#0,CY (A) ; (KOTAE+3)+=#0,CY (A) ; endif ; if(B != #15) (A) ; KOTAE+=KOTAE (A) ; KOTAE+1+=KOTAE+1,CY (A) ; KOTAE+2+=KOTAE+2,CY (A) ; KOTAE+3+=KOTAE+3,CY (A) ; endif ; next ; RET END Multiplicand area Multiplier area Work area Operation result storage area Stores multiplier (low) in work area Initializes operation result storage area Stores higher multiplier in work area if low multiplication is completed Shifts multiplier 1 bit to left Adds multiplicand to operation result storage area if carry occurs Shifts operation result storage area 1 bit to left 74 CHAPTER 2 FUNDAMENTALS OF SOFTWARE 2.8 Binary Division (32 bits / 16 bits) Data in a dividend area (HIWARU; 32 bits) is divided by data in a divisor area (WARUM; 16 bits), and the result is stored in an operation result storage area (KOTAE). If a remainder is generated, it is stored in a calculation result reminder area (AMARI). If division is executed with the divisor being 0, an error occurs. Figure 2-8. Binary Division HIWARU + 3 Dividend storage area (4 bytes) HIWARU / WARUM + 1 WARUM Divisor area (2 bytes) KOTAE + 3 Operation result storage area (4 bytes) = KOTAE AMARI + 1 Calculation result remainder area (2 bytes) AMARI 75 CHAPTER 2 FUNDAMENTALS OF SOFTWARE EXTRN EXTRN EXBIT MAIN: ; * * ; ; HIWARU=WORKA (A) ; HIWARU+1=WORKA+1 (A) WARUM=WORKB (A) ; ; WARUM+1=WORKB+1 (A) ; CALL !S_WARU HL=#KOTAE ; ; * ; * if_bit(F_ERR) ; Calculation error processing ; ; endif * * * S_WARU HIWARU,WARUM,KOTAE F_ERR Stores dividend data to dividend area Stores divisor data to divisor area Calls division calculation routine HL stores RAM address of operation result storage area Caution Manipulate the data memory in 8-bit units. 76 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (1) Input/output conditions * Input parameter HIWARU: Store the dividend data in this area. WARUM : Store the divisor data in this area. * Output parameter KOTAE : Store the result of the calculation in this area. (2) SPD chart [Division subroutine] S_WARU Clears operation error flag Initializes operation result storage area and calculation result remainder area if (divisor = #0) THEN Sets operation error flag if_bit (operation error flag = #0) THEN for (B = #0 ; B < #32 ; B + +) Shifts dividend and calculation result remainder I bit to left at same time if (calculation result remainder divisor) THEN Calculation result remainder calculation result remainder - divisor Dividend dividend OR #1 Operation result storage area dividend area (3) Registers used A, B 77 CHAPTER 2 FUNDAMENTALS OF SOFTWARE (4) Program list $PC(054) ; PUBLIC S_WARU,HIWARU,WARUM,F_ERR EXTRN KOTAE ; ;************************************************ ; RAM definition ;************************************************ DSEG SADDR ; HIWARU: DS 4 ; WARUM: DS 2 ; AMARI: DS 2 BSEG ; F_ERR DBIT ;************************************************ ; Division ;************************************************ ; CSEG ; S_WARU: ; CLR1 F_ERR ; AMARI=#0 ; AMARI+1=#0 ; KOTAE=#0 ; KOTAE+1=#0 ; KOTAE+2=#0 ; KOTAE+3=#0 ; if(WARUM == #0) ; if(WARUM+1 == #0) ; SET1 F_ERR ; endif ; endif ; if_bit(!F_ERR) ; for(B=#0;B < #32;B++) (A) ; HIWARU+=HIWARU (A) ; HIWARU+1+=HIWARU+1,CY (A) ; HIWARU+2+=HIWARU+2,CY (A) ; HIWARU+3+=HIWARU+3,CY (A) ; AMARI+=AMARI,CY (A) ; AMARI+1+=AMARI+1,CY (A) if(AMARI+1 > WARUM+1) (A) AMARI-=WARUM (A) AMARI+1-=WARUM+1,CY (A) HIWARU |= #1 elseif_bit(Z) if(AMARI >= WARUM) (A) AMARI-=WARUM(A) AMARI+1-=WARUM+1,CY (A) HIWARU |= #1 endif endif next KOTAE=HIWARU (A) KOTAE+1=HIWARU+1 (A) KOTAE+2=HIWARU+2 (A) KOTAE+3=HIWARU+3 (A) endif RET END Dividend area Divisor area Calculation result remainder storage area Operation error flag Clears operation error flag Clears calculation result storage area to 0 Clears operation result storage area to 0 Divisor = 0? Sets operation error flag if divisor is 0 Operation error? Starts 32-bit division Shifts dividend and remainder 1 bit to left ; ; Remainder divisor? ; Remainder = remainder - divisor ; ; Stores 1 to first bit of dividend area ; ; ; ; ; ; ; ; ; Stores operation result ; ; ; ; ; 78 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION The 78K/0 series allows you to select a CPU clock and controls the operation of the oscillator by rewriting the contents of the processor clock control register (PCC), oscillation mode select register (OSMS), and clock select registers 1 and 2 (IECL1 and IECL2). When the CPU clock is changed, the time shown in Table 3-1 is required since the contents of the PCC have been rewritten until the CPU clock is actually changed. It is therefore not apparent for a while after the contents of the PCC have been rewritten, whether the processor operates on the new or old clock. To stop the main system clock or execute the STOP instruction, therefore, the wait time shown in Table 3-1 is necessary. Caution IECL1 and IECL2 are provided to the PD78098, 78098B subseries only. 79 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Table 3-1. Maximum Time Required for Changing CPU Clock Set Value before Change Set Value after Change MCS CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 x 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction x 0 0 0 1 16 instructions 4 instructions 2 instructions 1 instruction 1 instruction x 0 0 1 0 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction x 0 0 1 1 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction x 0 1 0 0 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 1 1 x x x fX/2fXT instructions fX/4fXT instructions fX/8fXT instructions fX/16fXT instructions fX/32fXT instructions (77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions) 0 1 x x x fX/4XT instructions fX/8fXT instructions fX/16fXT instructions fX/32fXT instructions fX/64fXT instructions (3 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions) Caution Do not select dividing the CPU clock (PCC0-PCC2) and changing from the main system clock to subsystem clock (by setting CSS to 0 1) at the same time. However, dividing the CPU clock (PCC0-PCC2) can be selected at the same time as changing from the subsystem clock to the main system clock. Remarks 1. One instruction is the minimum instruction execution time of the CPU clock before change. 2. ( ): fX = 5.0 MHz, fXT = 32.768 kHz 80 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-1. Format of Processor Clock Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol PCC R/W 7 MCC CSS 6 FRC 5 CLS 4 CSS 3 0 2 1 0 Address FFFBH At reset 04H R/W R/W Note1 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 Selects CPU clock (fCPU) MCS = 1 MCS = 0 fX/2 fX/22 fX/23 fX/24 fX/25 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXT/2 fX fX/2 fX/22 fX/23 fX/24 1 0 0 0 0 1 Others Setting prohibited R CLS 0 1 Main system clock Subsystem clock Status of CPU clock R/W FRC 0 1 Selects feedback resistor of subsystem clock Uses internal feedback resistor Does not use internal feedback resistor Controls oscillation of main system clockNote 2 Enables oscillation Stops oscillation R/W MCC 0 1 Notes 1. Bit 5 is a read-only bit. 2. Use MCC to stop the oscillation of the main system clock when the CPU operates on the subsystem clock. Do not use the STOP instruction. Caution Be sure to clear bit 3 to 0. Remarks 1. fXX 2. fX 3. fXT : main system clock frequency (fX or fX/2) : main system clock oscillation frequency : subsystem clock oscillation frequency 4. MCS: bit 0 of oscillation mode select register (OSMS) 81 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-2. Format of Processor Clock Control Register (PD78083 subseries) Symbol PCC 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFBH At reset 04H R/W R/W PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 Selects CPU clock (fCPU) MCS = 1 MCS = 0 fX/2 fX/22 fX/23 fX/24 fX/25 0 0 0 0 1 Others 0 0 1 1 0 0 1 0 1 0 fXX fXX/2 fXX/22 fXX/23 fXX/24 Setting prohibited fX fX/2 fX/22 fX/23 fX/24 Caution Be sure to clear bits 3 through 7 to 0. Remarks 1. fXX 2. fX : main system clock frequency (fX or fX/2) : main system clock oscillation frequency 3. MCS: bit 0 of oscillation mode select register (OSMS) 82 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-3. Format of Processor Clock Control Register (PD78098, 78098B subseries) Symbol PCC 7 MCC 6 FRC 5 CLS 4 CSS 3 0 2 1 0 Address FFFBH At reset 04H R/W R/W Note 1 PCC2 PCC1 PCC0 R/W CSS 0 PCC2 PCC1 PCC0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 Setting prohibited fXX fXX/2 fXX/22 fXX/23 fXX/24 fXT/2 Selects CPU clock (fCPU) 1 0 0 0 0 1 Others R CLS 0 1 Main system clock Subsystem clock Status of CPU clock R/W FRC 0 1 Selects feedback resistor of subsystem clock Uses internal feedback resistor Does not use internal feedback resistor Controls oscillation of main system clockNote 2 Enables oscillation Stops oscillation R/W MCC 0 1 Notes 1. Bit 5 is a read-only bit. 2. Use MCC to stop the oscillation of the main system clock when the CPU operates on the subsystem clock. Do not use the STOP instruction. Caution Be sure to clear bit 3 to 0. Remarks 1. fXX : main system clock frequency 2. fXT : subsystem clock oscillation frequency 83 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-4. Format of Processor Clock Control Register (PD780018, 780018Y subseries) Symbol PCC 7 MCC 6 FRC 5 CLS 4 CSS 3 0 2 1 0 Address FFFBH At reset 04H R/W R/W Note 1 PCC2 PCC1 PCC0 R/W CSS 0 PCC2 PCC1 PCC0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 Setting prohibited fXX fXX/2 fXX/22 fXX/23 fXX/24 fXT/2 Selects CPU clock (fCPU) fX fX/2 fX/22 fX/23 fX/24 1 0 0 0 0 1 Others R CLS 0 1 Main system clock Subsystem clock Status of CPU clock R/W FRC 0 1 Selects feedback resistor of subsystem clock Uses internal feedback resistor Does not use internal feedback resistor Controls oscillation of main system clockNote 2 Enables oscillation Stops oscillation R/W MCC 0 1 Notes 1. Bit 5 is a read-only bit. 2. Use MCC to stop the oscillation of the main system clock when the CPU operates on the subsystem clock. Do not use the STOP instruction. Caution Be sure to clear bit 3 to 0. Remarks 1. fXX : main system clock frequency (fX) 2. fX : main system clock oscillation frequency 3. fXT : subsystem clock oscillation frequency 84 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-5. Format of Oscillation Mode Select Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol OSMS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MCS Address FFF2H At reset 00H R/W W MCS 0 1 Controls divider circuit of main system clock Uses divider circuit Does not use divider circuit Cautions 1. When an instruction that writes a value to the OSMS is executed (including when the instruction is executed to write the same value), the main system clock cycle is extended up to 2/fX only during the execution of the write instruction. Consequently, a temporary error of the count clock cycle of the peripheral hardware units that operate on the main system clock, such as timers, occurs. When the oscillation mode is changed, the clock supplied to the peripheral hardware, as well as the clock supplied to the CPU, is changed. It is therefore recommended that you execute the instruction to write the OSMS only once after the reset signal has been deasserted, and before the peripheral hardware operates. 2. Set 1 to MCS after VDD has risen to 2.7 V or more. Figure 3-6. Format of Oscillation Mode Select Register (PD78098, 78098B subseries) Symbol OSMS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MCS Address FFF2H At reset 00H R/W W MCS 0 1 Controls divider circuit of main system clock (divider circuit 1) Uses 1/2 divider circuit in divider circuit 1 Does not use 1/2 divider circuit in divider circuit 1 Caution When an instruction that writes a value to the OSMS is executed (including when the instruction is executed to write the same value), the main system clock cycle is extended up to 2/fX only during the execution of the write instruction. Consequently, rary error of the count clock cycle of the peripheral hardware units that operate on the main system clock, such as timers, occurs. When the oscillation mode is changed, the clock supplied to the peripheral hardware, as well as the clock supplied to the CPU, is changed. It is therefore recommended that you execute the instruction to write the OSMS only once after the reset signal has been deasserted, and before the peripheral hardware operates. 85 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-7. Format of Oscillation Mode Select Register (PD780018, 780018Y subseries) Symbol OSMS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MCS Address FFF2H At reset 00H R/W W MCS 0 1 Controls divider circuit of main system clock Setting prohibited Does not use divider circuit Cautions 1. When an instruction that writes a value to the OSMS is executed (including when the instruction is executed to write the same value), the main system clock cycle is extended up to 2/fX only during the execution of the write instruction. Consequently, a temporary error of the count clock cycle of the peripheral hardware units that operate on the main system clock, such as timers, occurs. 2. Setting MCS to 0 is prohibited. On RESET input, however, OSMS is reset to 00H. Therefore, be sure to set MCS to 1 at the start of a program or after clearing reset. Figure 3-8. Format of Clock Select Register 1 (PD78098, 78098B subseries) Symbol IECL1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address F8E0H At reset 00H R/W R/W IECL11 IECL10 IECL10 0 1 Controls divider circuit of main system clock (divider circuit 1) Uses 2/3 divider circuit in divider circuit 1 Does not use 2/3 divider circuit in divider circuit 1 IECL11 0 1 Controls divider circuit of main system clock (divider circuit 2) Uses 1/2 divider circuit in divider circuit 2 Does not use1/2 divider circuit in divider circuit 2 Caution Be sure to clear bits 2 through 7 to 0. Figure 3-9. Format of Clock Select Register 2 (PD78098, 78098B subseries) Symbol IECL2 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IECL20 Address F8E1H At reset 00H R/W R/W IECL20 0 1 Controls divider circuit of main system clock (divider circuit 1) Uses 1/3 divider circuit in divider circuit 1 Does not use 1/3 divider circuit in divider circuit 1 Caution Be sure to clear bits 1 through 7 to 0. 86 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION The fastest instruction is executed in two CPU clocks. Therefore, the relation between the CPU clock (fCPU) and minimum instruction execution time is as shown in Tables 3-2 and 3-3. Table 3-2. Relation between CPU Clock and Minimum Instruction Execution Time (other than PD78098 and 78098B subseries) CPU Clock (fCPU) fX fX/2 fX/22 fX/23 fX/24 fX/25Note 1 fXTNote 2 Minimum Instruction Execution Time: 2/fCPU 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s 122 s Notes 1. Except PD780018 and 780018Y subseries 2. Except PD78083 subseries Remark fX = 5.0 MHz, fXT = 32.768 kHz fX : Main system clock oscillation frequency fXT : Subsystem clock oscillation frequency 87 Table 3-3. CPU Clock (fCPU) List (PD78098 and 78098B Subseries) 88 Selects CPU clock (fCPU) CSS PCC2 PCC1 PCC0 MCS IECL20 IECL10 0 0 0 0 fXX 0 0 0 0 0 1 fXX/2 0 1 0 fXX/22 0 1 1 fXX/23 1 0 0 fXX/24 1 0 0 0 0 1 Others 0 0 1 1 0 0 1 0 1 0 Setting prohibited fXT/2(122 s) 0 0 1 (2fX/3)/2 (1.00 s) (2fX/3)/22 (2.00 s) (2fX/3)/23 (4.00 s) (2fX/3)/24 (8.00 s) (2fX/3)/25 (16.0 s) 0 1 0 (fX/3)/2 (2.00 s) (fX/3)/22 (4.00 s) (fX/3)/23 (8.00 s) (fX/3)/24 (16.0 s) (fX/3)/25 (32.0 s) 0 1 1 (2fX/9)/2 (3.00 s) (2fX/9)/22 (6.00 s) (2fX/9)/23 (12.0 s) (2fX/9)/24 (24.0 s) (2fX/9)/25 (48.0 s) 1 0 0 fX (Setting prohibited) 1 0 1 2fX/3 (0.50 s) (2fX/3)/2 (1.00 s) (2fX/3)/22 (2.00 s) (2fX/3)/23 (4.00 s) (2fX/3)/24 (8.00 s) 1 1 0 fX/3 (1.00 s) (fX/3)/2 (2.00 s) (fX/3)/22 (4.00 s) (fX/3)/23 (8.00 s) (fX/3)/24 (16.0 s) 1 1 1 2fX/9 CHAPTER 3 (1.50 s) (2fX/9)/2 (3.00 s) (2fX/9)/22 (6.00 s) (2fX/9)/23 (12.0 s) (2fX/9)/24 (24.0 s) fX/2 (0.67 s) fX/22 (1.33 s) fX/23 (2.67 s) fX/24 (5.33 s) fX/25 (10.7 s) fX/2 (0.67 s) fX/22 (1.33 s) fX/23 (2.67 s) fX/24 (5.33 s) APPLICATION OF SYSTEM CLOCK SELECTION Remarks 1. fX : Main system clock oscillation frequency 2. fXX : Main system clock frequency 3. fXT : Subsystem clock oscillation frequency 4. ( ) : Minimum instruction execution time with fX = 6.0 MHz or fXT = 32.768 kHz: 2/fCPU CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION 3.1 Changing PCC Immediately after RESET When the RESET signal is asserted, the slowest mode (processor clock control register: PCC = 04H, oscillation mode select register: OSMS = 00H) of the main system clock is selected for the CPU clock. To set the highest speed of the CPU clock, therefore, the contents of the PCC must be rewritten (PCC = 00H, OSMS = 01H). To use the fasted mode, however, the voltage on the VDD pin has to have risen to a sufficient level and be stable. In the following example, the CPU waits until the VDD pin voltage has risen to the sufficient level by using the watch timer (the interval time is set to 3.91 ms). After that, the CPU operates on the fastest clock. Figure 3-10. Example of Selecting CPU Clock after RESET (with PD78054 subseries) Commercial power source ON OFF 4.5 V VDD pin voltage 2.0 V H RESET signal L CPU clock wait time Wait status 31.3 ms (217/fX: at 4.19 MHz) 15.28 s 3.9 ms 0.48 s RESET signal is deasserted 10 s after VDD pin voltage has risen to 2.0 V or more. CPU clock oscillation starts. VDD pin voltage has risen to 4.5 V or more before contents of PCC are changed. 89 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION (1) SPD chart Sets watch timer to 3.91 ms WHILE: No watch timer interrupt request ( ! TMIF3) Clears TMIF3 Sets PCC in fastest mode (2) Program list ;************************************** ;* Sets wait time ;************************************** TCL2=#00010000B ; Sets watch timer to 3.91 ms TMC2=#00110110B ; 3.91 ms? while_bit(!TMIF3) endw CLR1 WTIF ; Does not use divider circuit OSMS=#00000001B ; Sets CPU clock in fastest mode PCC=#00000000B 90 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION 3.2 Selecting Power ON/OFF The 78K/0 series can operate in an ultra low current consumption mode by using the processor clock control register (PCC) and selecting the subsystem clock. By providing a backup power supply such as a Ni-Cd battery or super capacitor to the system, therefore, the system can continue operating even if a power failure occurs. In this example, a power failure is detected by using INTP1 (both the rising and falling edges are selected as the edge to be detected), and the contents of the PCC are changed depending on the port level at that time. Figure 311 shows a circuit example, and Figure 3-12 shows the system clock changing timing. Figure 3-11. Example of System Clock Changing Circuit + 5.6V + VDD VSS INTP1/TI01/P01 PD78054 91 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION Figure 3-12. Example of Changing System Clock on Power Failure (PD78054 subseries) 6.0 (V) VDD pin voltage 4.5 (V) 2.0 (V) ON OFF H P01/INTP1 pin L Interrupt request occurs System clock Main system clock Interrupt request occurs Main system clock Commercial power source Subsystem clock Waits until VDD rises to 4.5 V or more 92 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION (1) SPD chart INTP1 IF: power off (P01 = low level) THEN Sets CPU clock in slowest mode User processing ELSE Sets CPU clock in fastest mode User processing (2) Program list VEP0 CSEG DW MOV CLR1 EI AT 08H INTP1 INTM0,#00110000B PMK1 ; Sets vector address of INTP1 ; Both edge detection mode ;***************************************** ;* Sets low-/high-speed mode ;***************************************** INTP1: if_bit(!P0.1) ; Setting of internal hardware (low speed) ; User processing PCC=#10010000B ; Sets low-speed mode ; ; else Sets internal hardware (high speed) User processing PCC=#00000000B endif RETI ; Sets high-speed mode 93 [MEMO] 94 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER The watchdog timer of the 78K/0 series has two modes: watchdog timer mode in which a hang-up of the microcontroller is detected, and interval timer mode. The watchdog timer is set by using timer clock select register 2 (TCL2) and watchdog timer mode register (WDTM). 95 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-1. Format of Timer Clock Select Register 2 (PD78054 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol 7 6 5 4 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Selects count clock of watchdog timer MCS = 1 MCS = 0 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) (1.2 kHz) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (2.4 kHz) fX/210 fX/212 fX/211 TCL24 Selects count clock of watch timer MCS = 1 MCS = 0 fX/28 (19.5 kHz) 0 1 fXX/27 fXT (32.768 kHz) fX/27 (39.1 kHz) TCL27 TCL26 TCL25 Selects frequency of buzzer output MCS = 1 MCS = 0 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 fXX/210 fXX/211 Setting prohibited fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) fX/212 (1.2 kHz) Caution To change the data of TCL2 except when writing the same data, once stop the timer operation. Remarks 1. fXX 2. fX 3. fXT 4. x : main system clock frequency (fX or fX/2) : main system clock oscillation frequency : subsystem clock oscillation frequency : don't care 5. MCS: bit 0 of oscillation mode select register (OSMS) 6. ( ) : fX = 5.0 MHz or fXT = 32.768 kHz 96 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-2. Format of Timer Clock Select Register 2 (PD78083 subseries) Symbol 7 6 5 4 0 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Selects count clock of watchdog timer MCS = 1 MCS = 0 fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/212 (1.2 kHz) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) TCL27 TCL26 TCL25 Selects frequency of buzzer output MCS = 1 MCS = 0 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 fXX/210 fXX/211 Setting prohibited fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) fX/212 (1.2 kHz) Cautions 1. To change the data of TCL2 except when writing the same data, once stop the timer operation. 2. Be sure to clear bits 3 and 4 to 0. Remarks 1. fXX 2. fX 3. x 5. ( : main system clock frequency (fX or fX/2) : main system clock oscillation frequency : don't care ) : fX = 5.0 MHz 4. MCS: bit 0 of oscillation mode select register (OSMS) 97 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-3. Format of Timer Clock Select Register 2 (PD78098, 78098B subseries) Symbol 7 6 5 4 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 Selects count clock of watchdog timer fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) fXX/29 (7.8 kHz) fXX/211 (2.0 kHz) TCL24 0 1 fXX/27 (31.3 kHz) fXT (32.768 kHz) Selects count clock of watch timer TCL27 TCL26 TCL25 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 (7.8 kHz) fXX/210 (3.9 kHz) fXX/211 (1.95 kHz) Setting prohibited Selects frequency of buzzer output Caution To change the data of TCL2 except when writing the same data, once stop the timer operation. Remarks 1. fXX : main system clock frequency 2. fXT : subsystem clock oscillation frequency 3. x : don't care 4. ( ) : fXX = 4.0 MHz or fXT = 32.768 kHz 98 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-4. Format of Timer Clock Select Register 2 (PD780018, 780018Y subseries) Symbol 7 6 5 4 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 TCL22 TCL21 TCL20 Selects count clock of watchdog timer fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) TCL24 0 1 fXX/27 fXT (32.768 kHz) Selects count clock of watch timer fX/27 (39.1 kHz) TCL27 TCL26 TCL25 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 fXX/210 fXX/211 Setting prohibited Selects frequency of buzzer output fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) Caution To change the data of TCL2 except when writing the same data, once stop the timer operation. Remarks 1. fXX : main system clock frequency (fX) 2. fX : main system clock oscillation frequency 3. fXT : subsystem clock oscillation frequency 4. x : don't care 5. ( ): fX = 5.0 MHz or fXT = 32.768 kHz 99 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER Figure 4-5. Format of Watchdog Timer Mode Register Symbol WDTM 7 RUN 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H At reset 00H R/W R/W WDTM4 WDTM3 WDTM4 WDTM3 Selects operation mode of watchdog time Note 2 Note 1 0 1 1 x 0 1 Interval timer mode (maskable interrupt request occurs when overflow occurs) Watchdog timer mode (non-maskable interrupt request occurs when overflow occurs) Watchdog timer mode 2 (reset operation starts when overflow occurs) RUN 0 1 Selects watchdog timer operationNote 3 Stops counting Clears counter and starts counting Notes 1. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software. 2. When RUN is set to 1, the WDTM starts interval timer operation. 3. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting has been started, it cannot be stopped by any means other than the RESET signal. Caution 1. When RUN is set to 1 and the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the timer clock select register 2. 2. When using the watchdog timer modes 1 and 2, confirm that the interrupt request flag (TMIF4) is 0 and then set WDTM4 to 1. If WDTM4 is set to 1 while TMIF4 is 1, the non-maskable interrupt occurs regardless of the contents of WDTM3. 100 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER 4.1 Setting Watchdog Timer Mode Reset processing or non-maskable interrupt processing is performed after the watchdog timer has detected a hangup. You can select which processing is to be performed by the watchdog timer mode register (WDTM). When the watchdog timer mode is used, the timer must be cleared at intervals shorter than the set hang-up detection time. If the timer is not cleared, an overflow occurs, and reset or interrupt processing is executed. The hang-up detection time of the watchdog timer is set by the timer clock select register 2 (TCL2). In the following example, the hang-up detection time is set to 7.81 ms and the reset processing is performed when an overflow occurs. (1) SPD chart Sets hang-up detection time of watchdog timer to 7.81 ms Sets watchdog timer in reset start mode User processing 1 Clears watchdog timer User processing 2 Clears watchdog timer User processing 3 Clears watchdog timer 101 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER (2) Program list ;************************************* ;* Sets watchdog timer ;************************************* OSMS=#00000001B TCL2=#00000100B WDTM=#10011000B ; User processing 1 ; Does not use divider circuit ; Sets watchdog timer to 7.81 ms ; Sets reset start mode -- -- SET1 ; RUN ; Clears timer User processing 2 -- -- SET1 ; RUN ; Clears timer User processing 3 -- -- SET1 RUN ; Clears timer 102 -- CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER 4.2 Setting Interval Timer Mode When the interval timer mode is used, the interval time is set by the timer clock select register 2 (TCL2) (interval time = 0.488 ms to 125 ms, at fX = 4.19 MHz). In this mode, an interrupt request flag (TMIF4) is set when an overflow occurs in the timer. In the following example, three types of times, 0.977 ms, 7.82 ms, and 125 ms, are set. Figure 4-6. Count Timing of Watchdog Timer Timer count INTWDT FC FD FE FF 00 01 02 03 FD FE FF 00 (1) Program list <1> To set 0.977 ms TCL2=#00000001B WDTM=#10001000B <2> To set 7.82 ms TCL2=#00000100B WDTM=#10001000B <3> To set 125 ms TCL2=#00000111B WDTM=#10001000B ; Sets 125 ms ; Selects interval timer mode ; Sets 7.82 ms ; Selects interval timer mode ; Sets 0.977 ms ; Selects interval timer mode Remark The above interval time is the value when OSMS = 01H. 103 [MEMO] 104 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER The 16-bit timer/event counter of the 78K/0 series has the following six functions: * Interval timer * PWM output * Pulse width measurement * External event counter * Square wave output * One-shot pulse output The 16-bit timer/event counter is set by the following registers: * Timer clock select register 0 (TCL0) * 16-bit timer mode control register (TMC0) * Capture/compare control register 0 (CRC0) * 16-bit timer output control register (TOC0) * Port mode register 3 (PM3) * External interrupt mode register (INTM0) * Sampling clock select register (SCS) 105 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-1. Format of Timer Clock Select Register 0 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol TCL0 7 6 5 4 3 2 1 0 Address FF40H At reset 00H R/W R/W CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 TCL03 TCL02 TCL01 TCL00 Selects clock of PCL output MCS = 1 MCS = 0 0 0 0 0 1 1 1 1 1 Others 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXT (32.768 kHz) fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 Setting prohibited fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) TCL06 TCL05 TCL04 Selects count clock of 16-bit timer register MCS = 1 MCS = 0 0 0 0 0 1 1 Others 0 0 1 1 0 1 0 1 0 1 0 1 TI00 (valid edge can be specified) 2fXX fXX fXX/2 fXX/22 Setting prohibited fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) Watch timer output (INTTM3) Setting prohibited CLOE 0 1 Disables output Enables output Controls PCL output Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0 (INTM0). The frequency of the sampling clock is selected by the sampling clock select register (SCS). 2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit memory manipulation instruction. 3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00 is specified as the count clock of TM0. 4. Before writing new data to TCL0, stop the timer operation once. 106 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Remarks 1. fXX 2. fX 3. fXT : main system clock frequency (fX or fX/2) : main system clock oscillation frequency : subsystem clock oscillation frequency 4. TI00 : input pin of 16-bit timer/event counter 5. TM0 : 16-bit timer register 6. MCS: bit 0 of oscillation mode select register (OSMS) 7. ( ) : at fX = 5.0 MHz or fXT = 32.768 kHz 107 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-2. Format of Timer Clock Select Register 0 (PD78098, 78098B subseries) Symbol TCL0 7 6 5 4 3 2 1 0 Address FF40H At reset 00H R/W R/W CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 TCL03 TCL02 TCL01 TCL00 0 0 0 0 1 1 1 1 1 Others 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXT (32.768 kHz) fXX (4.0 MHz) fXX/2 (2.0 MHz) fXX/22 (1.0 MHz) fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) Setting prohibited Selects clock of PCL output TCL06 TCL05 TCL04 0 0 0 0 1 1 Others 0 0 1 1 0 1 0 1 0 1 0 1 Selects count clock of 16-bit timer register TI00 (valid edge can be specified) 2fXXNote fXX (4.0 MHz) fXX/2 (2.0 MHz) fXX/22 (1.0 MHz) Watch timer output (INTTM3) Setting prohibited CLOE 0 1 Disables output Enables output Controls PCL output Note At fXX > 2.5 MHz, setting prohibited. Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0 (INTM0). The frequency of the sampling clock is selected by the sampling clock select register (SCS). 2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit memory manipulation instruction. 3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00 is specified as the count clock of TM0. 4. Before writing new data to TCL0, stop the timer operation once. Remarks 1. fXX 2. fXT : main system clock frequency : subsystem clock oscillation frequency 3. TI00 : input pin of 16-bit timer/event counter 4. TM0 : 16-bit timer register 5. ( ) : at fXX = 4.0 MHz or fXT = 32.768 kHz 108 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-3. Format of Timer Clock Select Register 0 (PD780018, 780018Y subseries) Symbol TCL0 7 6 5 4 3 2 1 0 Address FF40H At reset 00H R/W R/W CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 TCL03 TCL02 TCL01 TCL00 0 0 0 0 1 1 1 1 1 Others 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXT (32.768 kHz) fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 Setting prohibited Selects clock of PCL output fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) TCL06 TCL05 TCL04 0 0 0 1 1 Others 0 1 1 0 1 0 0 1 0 1 Selects count clock of 16-bit timer register TI00 (valid edge can be specified) fXX fXX/2 fXX/22 Watch timer output (INTTM3) Setting prohibited fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) CLOE 0 1 Disables output Enables output Controls PCL output Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0 (INTM0). The frequency of the sampling clock is selected by the sampling clock select register (SCS). 2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit memory manipulation instruction. 3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00 is specified as the count clock of TM0. 4. Before writing new data to TCL0, stop the timer operation once. Remarks 1. fXX 2. fX 3. fXT : main system clock frequency (fX) : main system clock oscillation frequency : subsystem clock oscillation frequency 4. TI00 : input pin of 16-bit timer/event counter 5. TM0 : 16-bit timer register 6. ( ) : at fX = 5.0 MHz or fXT = 32.768 kHz 109 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-4. Format of 16-Bit Timer Mode Control Register Symbol TMC0 7 0 6 0 5 0 4 0 3 2 1 0 Address FF48H At reset 00H R/W R/W TMC03 TMC02 TMC01 OVF0 OVF0 0 1 Overflow does not occur Overflow occurs Detects overflow of 16-bit timer register TMC03 TMC02 TMC01 Selects operation mode and clear mode Stops operation (clears TM0 to 0) PWM mode (free running) Free running mode Selects output timing of TO0 Occurrence of interrupt request Does not occur 0 0 0 Not affected 0 0 0 1 1 0 PWM pulse output Coincidence between TM0 and CR00 or between TM0 and CR01 Occurs if TM0 and CR00 coincide and if TM0 and CR01 coincide 0 1 1 Coincidence between TM0 and CR00, or between TM0 and CR01, or valid edge of TI00 Clears and starts at valid edge of TI00 Coincidence between TM0 and CR00 or between TM0 and CR01 Coincidence between TM0 and CR00, or between TM0 and CR01, or valid edge of TI00 Clears and start at coincidence between TM0 and CR00 Coincidence between TM0 and CR00 or between TM0 and CR01 Coincidence between TM0 and CR00, or between TM0 and CR01, or valid edge of TI00 1 0 0 1 0 1 1 1 0 1 1 1 Cautions 1. Before setting the clear mode or changing the output timing of TO0, stop the timer operation (by clearing TMC01 through TMC03 to 0, 0, 0). 2. The valid edge of the TI00/INTP0 pin is selected by the external interrupt mode register 0 (INTM0). The frequency of the sampling clock is selected by the sampling clock select register (SCS). 3. When using the PWM mode, set data to CR00 after setting the PWM mode. 4. When a mode in which the timer is cleared and started on coincidence between TM0 and CR00, the OVF0 flag is set to 1 when the set value of CR00 is FFFFH and the value of TM0 changes from FFFFH to 0000H. 5. The 16-bit timer register starts operating as soon as a value other than 0, 0, 0 (operation stop mode) is set to TMC01 through TMC03. To stop the operation, clear TMC01 through TMC03 to 0, 0, 0. 110 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Remarks 1. TO0 2. TI00 3. TM0 : output pin of 16-bit timer/event counter : input pin of 16-bit timer/event counter : 16-bit timer register 4. CR00 : compare register 00 5. CR01 : compare register 01 Figure 5-5. Format of Capture/Compare Control Register Symbol CRC0 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FF4CH At reset 04H R/W R/W CRC02 CRC01 CRC00 CRC00 Selects operation mode of CR00 0 1 Operates as compare register Operates as capture register CRC01 Selects capture trigger of CR00 0 1 Captures at valid edge of TI01 Captures at valid edge of TI00 CRC02 Selects operation mode of CR01 0 1 Operates as compare register Operates as capture register Cautions 1. Be sure to stop the timer operation before setting CRC0. 2. When a mode in which the timer is cleared and started on coincidence between TM0 and CR00 is selected by the 16-bit timer mode control register, do not specify CR00 as the capture register. 111 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-6. Format of 16-Bit Timer Output Control Register Symbol TOC0 7 0 6 5 4 3 2 1 0 Address FF4EH At reset 00H R/W R/W OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOE0 0 1 Controls output of 16-bit timer/event counter Disables output (port mode) Enables output TOC01 PWM mode Selects active level Other than PWM mode Controls timer output F/F on coincidence between CR00 and TM0 Disables reverse operation 0 1 Active high Active low Enables reverse operation LVS0 0 0 0 0 LVR0 0 1 0 1 Sets status of timer output F/F of 16-bit timer/ event counter Not affected Resets timer output F/F (to 0) Sets timer output F/F (to 1) Setting prohibited TOC04 Controls timer output F/F on coincidence between CR01 and TM0 0 0 Disables reverse operation Enables reverse operation OSPE 0 1 Controls one-shot pulse output operation Successive pulse output One-shot pulse output OSPT 0 1 Controls output trigger of one-shot pulse by software No one-shot pulse trigger One-shot pulse trigger Cautions 1. Be sure to stop the timer operation before setting TOC0 (except OSPT). 2. LVS0 and LVR0 are always 0 when they are read immediately after data has been set. 3. OSPT is automatically cleared after data has been set. It is therefore always 0 when read. 112 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-7. Format of Port Mode Register 3 Symbol PM3 7 6 5 PM35 4 PM34 3 PM33 2 PM32 1 0 Address FF23H At reset FFH R/W R/W PM37 PM36 PM31 PM30 PM3n 0 1 Selects input/output mode of P3n pin (n = 0-7) Output mode (output buffer ON) Input mode (output buffer OFF) Figure 5-8. Format of External Interrupt Mode Register 0 Symbol INTM0 7 ES31 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 0 0 0 Address FFECH At reset 00H R/W R/W ES11 0 0 1 1 ES10 0 1 0 1 Selects valid edge of INTP0 Falling edge Rising edge Setting prohibited Both rising and falling edges ES21 0 0 1 1 ES20 0 1 0 1 Selects valid edge of INTP1 Falling edge Rising edge Setting prohibited Both rising and falling edges ES31 0 0 1 1 ES30 0 1 0 1 Selects valid edge of INTP2 Falling edge Rising edge Setting prohibited Both rising and falling edges Caution Before setting the valid edge of the INTP0/TI00/P00 pin, clear bits 1 through 3 (TMC01 through TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, and stop the timer. 113 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-9. Format of Sampling Clock Select Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H At reset 00H R/W R/W SCS1 SCS0 SCS1 SCS0 Selects sampling clock of INTP0 MCS = 1 MCS = 0 fX/28 (19.5 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fXX/2N fXX/2 fXX/2 7 5 0 0 1 1 0 1 0 1 fX/27 (39.1 kHz) fX/2 (156.3 kHz) fX/26 (78.1 kHz) 5 fXX/26 Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are the clocks supplied to the peripheral hardware. fXX/2N is stopped in the HALT mode. Remarks 1. N 2. fXX 3. fX : Value (N = 0 to 4) set to the bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC) : main system clock frequency (fX or fX/2) : main system clock oscillation frequency 4. MCS: bit 0 of oscillation mode select register (OSMS) 5. ( ) : at fX = 5.0 MHz 114 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-10. Format of Sampling Clock Select Register (PD78098, 78098B subseries) Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H At reset 00H R/W R/W SCS1 SCS0 SCS1 0 0 1 1 SCS0 0 1 0 1 Selects sampling clock of INTP0 fXX/2N fXX/27 (31.3 kHz) fXX/2 (125.0 kHz) fXX/26 (62.5 kHz) 5 Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are the clocks supplied to the peripheral hardware. fXX/2N is stopped in the HALT mode. Remarks 1. N : Value (N = 0 to 4) set to the bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC) 2. fXX : main system clock frequency 3. ( ) : at fXX = 4.0 MHz Figure 5-11. Format of Sampling Clock Select Register (PD780018, 780018Y subseries) Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H At reset 00H R/W R/W SCS1 SCS0 SCS1 0 0 1 1 SCS0 0 1 0 1 Selects sampling clock of INTP0 fXX/2N fXX/27 fXX/2 fXX/2 5 6 7 fX/2 (39.1 kHz) fX/25 (156.3 kHz) fX/2 (78.1 kHz) 6 Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are the clocks supplied to the peripheral hardware. fXX/2N is stopped in the HALT mode. Remarks 1. N : Value (N = 0 to 4) set to the bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC) 2. fXX : main system clock frequency (fX) 3. fX : main system clock oscillation frequency 4. ( ) : at fX = 5.0 MHz 115 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.1 Setting of Interval Timer To set the 16-bit timer/event counter as an interval timer, first set the timer clock select register 0 (TCL0) and the 16-bit timer mode control register (TMC0). The clear mode of the 16-bit timer is set by TMC0 and the interval time is set by TCL0. After that, set the value of the compare register (CR00) from the setup time and count clock. Determine the setup time by using the following expression: Setup time = (Compare register value + 1) x Count clock cycle This section shows two examples of setup times of the interval timer: 10 ms and 50 ms. (a) Interval of 10 ms <1> Setting of TMC0 Selects a mode in which the timer is cleared and started on coincidence between TM0 and CR00. <2> Setting of TCL0 Select the fXX mode in which an interval time of 10 ms or more can be set and the resolution is the highest (OSMS = 01H). <3> Setting of CR00 10 ms = (N + 1) x 1 4.19 MHz N = 10 ms x 4.19 MHz - 1 *= 4.1899 * (1) Program list OSMS = #00000001B ; Does not use divider circuit CRC0 = #00000000B ; Selects CR00 as compare register CR00 = #41899 TCL0 = #00100000B ; Selects count clock fXX TMC0 = #00001100B ; Clears and starts 16-bit timer/event counter when TM0 and CR00 coincide 116 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (b) Interval of 50 ms <1> Setting of TMC0 Selects a mode in which the timer is cleared and started on coincidence between TM0 and CR00. <2> Setting of TCL0 Select the fXX/22 mode in which an interval time of 50 ms or more can be set and the resolution is the highest (OSMS = 01H). <3> Setting of CR00 50 ms = (N + 1) x 1 4.19 MHz/22 * N = 50 ms x 4.19 MHz/22 - 1 = * 52374 (1) Program list OSMS = #00000001B ; Does not use divider circuit CRC0 = #00000000B ; Selects CR00 as compare register CR00 = #52374 TCL0 = #01000000B ; Selects count clock fXX/22 TMC0 = #00001100B ; Clears and starts 16-bit timer/event counter when TM0 and CR00 coincide 117 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.2 PWM Output When using the 16-bit timer/event counter in the PWM output mode, set the PWM mode by the 16-bit timer mode control register (TMC0) and enables the output of the 16-bit timer/event counter by the 16-bit timer output control register (TOC0). The pulse width (active level) of PWM is determined by the value set to the capture/compare register 00 (CR00). Because the PWM of the 78K/0 series has a resolution of 14 bits, however, bits 2 through 15 of CR00 are valid (clear bits 0 and 1 of CR00 to `0, 0'). 1 x 28) and the low level is selected fXX as the active level. The high-order 4 bits of the pulse width are rewritten depending on the value of the parameter In the example below, the basic cycle of the PWM mode is set to 61.0 s ( (00H to FFH). Therefore, in the following application example, PWM output can be performed in 16 steps (CR00 = 0FFCH to FFFCH). (1) Description of package 118 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER . . . OSMS = #00000001B CRC0 = #00000000B TOC0 = #00000011B TCL0 = #00100000B TMC0 = #00000010B . . . PWMOUT = A CALL (3) SPD chart PWM !PWM Loads data of PWMOUT Decodes data of high-order 4 bits of CR00 Sets XFFCH to CR00 (X: 0 to FH) 119 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC PWM,PWMOUT PWM_DAT DSEG SADDR ; PWM output data area (0-15) PWMOUT: DS 1 ;************************************ ;* PWM output (16 steps) ;************************************ P0_SEG CSEG PWM: ; Loads high-order data of PWMOUT A=PWMOUT A<<=1 A<<=1 A<<=1 A<<=1 ; Sets low-order 12 bits to 0FFCH A|=#0FH X=#0FCH CR00=AX RET 120 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.3 Remote Controller Signal Reception This section introduces two examples of programs that receives signals from a remote controller by using the 16bit timer/event counter. * The counter is cleared each time the valid edge of the remote controller signal has been detected, and measures a pulse width from the timer count value (capture register CR01) when the next valid edge has been detected. * The timer operates in the free running mode to measure a pulse width from the difference of the counter between valid edges. PWM output is also performed at the same time. The remote controller signal is received by a PIN receiver diode and is input to the P00/TI00/INTP0 pin via receive amplifier PC1490. Figure 5-12 shows an example of a remote controller signal receiver circuit, and Figure 5-13 shows the format of the remote controller signal. Figure 5-12. Example of Remote Controller Signal Receiver Circuit +5 V + 160 k PH310 f0 IN+ PC1490 100 F 100 k VDD VCC OUT INTP0/TI00/P00 PD78054 IN- CD GND C1 4.7 + 1 F + 10 F 1000 pF GND Shield case 121 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-13. Remote Controller Signal Transmitter IC Output Signal Time at oscillation frequency of 455 kHz 67.5 ms 108 ms 108 ms 9 ms 4.5 ms Custom Code 8 bits Custom Code 8 bits Data Code 8 bits Data Code 8 bits 27 ms 67.5 ms 13.5 ms Leader Code 27 ms First time 9 ms 13.5 ms 4.5 ms 0.56 ms 1.125 ms 2.25 ms 0 1 Second time and onward (signal transmitted only while key is held down) 1 0 0 1 9 ms 11.25 ms 2.25 ms 0.56 ms Because the receiver preamplifier PC1490 used in the circuit example on the previous page is low-active, the level input to the PD78054 subseries is the inverted data of the remote controller transmit data. Figure 5-14. Output Signal of Receiver Preamplifier H PC1490 output L 9 ms 4.5 ms Leader code 122 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.3.1 Remote controller signal reception by counter clearing Table 5-1 shows the valid pulse width for receiving a remote controller signal in the program example shown in this section, and <1> through <6> describes how to process each signal. The repeat signal of the remote controller signal is valid only within 250 ms after a valid signal has been input. If a signal input within 3 ms after the normal data has been loaded, the data is invalid. Table 5-1. Valid Time of Input Signal Signal Name Leader code (low) Leader code (high) Custom/data code Normal Repeat 0 1 Output Time 9 ms 4.5 ms 2.25 ms 1.125 ms 2.25 ms Valid Time 6.8 ms-11.8 ms 3 ms-5 ms 1.8 ms-3 ms 0.5 ms-1.8 ms 1.8 ms-2.5 ms <1> Leader code (low) The interval time of the 16-bit timer/event counter is set to 1.5 ms, and the port level is sampled by means of interrupt processing. When five low levels have been detected in succession, these low levels are identified as a leader code, and the interval time is changed to 7.81 ms. After that, the pulse width of the low level of the leader code is measured by using rising-edge interrupt request INTP0. Figure 5-15. Sampling of Remote Controller Signal Valid if low five times in succession Noise Noise Interval time 1.5 ms 7.81 ms 123 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <2> Leader code (high) The pulse width while the leader code is high is measured by using the falling-edge interrupt request INTP0 and the count value of the timer. <3> Custom/data code The pulse width of each 1 bit (1 cycle) is measured by using the falling-edge interrupt request INTP0. After the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide. It also checks that there is no data in the 33rd bit. <4> Repeat code detection When the high level of the leader code is less than 3 ms, the pulse width from output of the leader code to the rising edge of the INTP0 is measured. <5> Valid period of repeat code After the valid data has been input, sampling is performed by the interrupt processing (1.5 ms interval) of the 16-bit timer/event counter to measure the valid time of the repeat code of 250 ms. <6> Time out during pulse width measurement If the interrupt request of the 16-bit timer/event counter (7.81 ms) occurs during pulse width measurement, it is judged to be time out, and the data is invalid. (1) Description of package RMDTOK : Input signal validity identification flag RMDTSET : Input signal identification flag 124 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER * Defines custom code to be CSTM and declares PUBLIC 125 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use PUBLIC CSTM EXTRN RMDATA,RPTCT EXTBIT RPT,RMDTSET,IPDTFG CSTM EQU 9DH ; Remote controller custom code ; Does not use divider circuit ; Selects operation mode of CR00, CR01 ; Sets 1.5 ms ; fXX/26 as INTP0 sampling clock ; INTP0 with high priority ; Clears flag OSMS=#00000001B CRC0=#00000100B CR00=#6290 TCL0=#00100000B TMC0=#00001100B SCS=#00000011B CLR1 CLR1 CLR1 CLR1 CLR1 EI PPR0 RPT IPDTFG RMDTSET TMMK0 ; Enables timer interrupt DT_TEST: if_bit(RMDTSET) CLR1 RMDTSET if_bit(RPT) ; ; Repeat processing ; else ; ; Processing when there is input ; endif else if_bit(!RPT) ; ; Processing when there is no input ; endif endif 126 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (3) SPD chart INTTM00 Selects register bank 1 Enables master interrupt IF: input signal exists (IPDTFG) THEN IF: valid data exists (RMDTOK) THEN IF: no input within repeat valid time (250 ms) THEN Invalidates repeat code ELSE Clears RPT, IPDTFG, and RMDTOK Counts repeat valid time Counts leader low time S_LOWCT ELSE IF: No input after end of data input (within 4.5 ms) THEN Valid data exists Sets RMDTOK and RMDTSET Sets leader low detection mode S_M0SET Initializes leader low detection counter ELSE Counts leader low time S_LOWCT S_LOWCT IF: Leader low detection mode THEN IF: P00 = LOW THEN IF: P00 = LOW five times in succession THEN Selects leader low measuring mode Sets 16-bit timer to 7.81 ms Sets INTP0 rising-edge detection mode Enables INTP0 Initializes leader low detection counter ELSE Initializes leader detection counter ELSE Sets leader low detection mode S_M0SET Initializes leader detection counter 127 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER INTP0 Selects register bank 0 Waits for 100 s WAIT CASE: SELMOD OF: 1 Leader low measuring mode LEAD_L OF: 2 Leader high measuring mode LEAD_H OF: 3 Custom code/data loading mode CDCODE OF: 4 Repeat code detection mode REPCD OF: 5 Abnormal data detection mode ENDCHK LEAD_L IF: P00 = HIGH THEN Waits for 100 s WAIT IF: P00 = HIGH THEN Reads timer CR_READ IF: 6.8 ms Ieader low 11.8 ms THEN Selects leader high detection mode Sets INTP0 falling-edge detection mode ELSE Sets leader low detection mode S_M0SET LEAD_H IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Reads timer CR_READ IF: 2 ms leader high 5 ms THEN IF: Ieader high 3 ms THEN Selects custom code/data load mode Initializes data storage area ELSE Selects repeat detection mode Sets INTP0 rising-edge detection mode ELSE Sets leader low detection mode S_M0SET 128 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CDCODE IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Reads timer CR_READ IF: 0.5 ms < input data 2.5 ms THEN IF: input data 1.8 ms THEN Sets CY ELSE Clears CY Stores CY to data storage area IF: end of 32 bits of data input THEN IF: custom code coincides THEN IF: custom/data code coincides with inverted data THEN Stores data code Sets status in which input data exists Sets IPDTFG and clears RMDTSET, RPT, and RMDTOK Sets leader low detection mode S_M0SET ELSE Sets leader low detection mode S_M0SET ELSE Sets leader low detection mode S_M0SET ELSE Sets leader low detection mode S_M0SET REPCD IF: P00 = HIGH THEN Waits for 100 s WAIT IF: P00 = HIGH THEN IF: valid data exists THEN Reads timer CR_READ IF: repeat code 1 ms THEN Sets repeat code valid status Sets RPT Sets data input end status Sets abnormal data detection mode S_M5SET ELSE Sets leader low detection mode S_M0SET ELSE Sets abnormal data detection mode S M5SET 129 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ENDCHK IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Sets input signal invalid status Clears IPDTFG and RPT Sets leader low detection mode S_M0SET CR_READ Reads capture register Stops 16-bit timer operation Starts timer S_M0SET Selects leader low detection mode Disables INTP0 interrupt Sets 16-bit timer to 1.5 ms S_M5SET Selects abnormal data detection mode Sets counter for repeat valid time Sets 16-bit timer to 1.5 ms 130 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC PUBLIC EXTRN RM_DAT DSEG RPTCT: DS RMENDCT: SELMOD: DS LD_CT: DS RMDATA: DS RM_DATP DSEG WORKP: DS BSEG IPDTFG DBIT RMDTOK DBIT RMDTSET DBIT RPT DBIT VEP0 CSEG DW CSEG DW AT 06H INTP0 AT 20H INTTM00 RPT,IPDTFG,RMDTOK,RMDTSET RMENDCT,RPTCT,SELMOD,LD_CT,RMDATA CSTM SADDR 1 DS 1 1 1 SADDRP 4 ; ; ; ; ; Repeat code valid time counter No-input time counter after data input 1 Selects mode Leader signal detection counter Valid data storage area ; Input signal storage area ; ; ; ; Valid data exists Input signal is valid Input signal exists Repeat code valid period ; Sets vector address of INTP0 VETM0 ; Sets vector address of 16-bit timer ;****************************************************** ; Remote controller signal timer processing ;****************************************************** TM0_SEG CSEG INTTM00: SEL RB1 EI if_bit(IPDTFG) if_bit(RMDTOK) RPTCT-- if(RPTCT==#0) CLR1 RPT CLR1 IPDTFG CLR1 RMDTOK endif CALL !S_LOWCT else RMENDCT-- if(RMENDCT==#0) SET1 RMDTOK SET1 RMDTSET CALL !S_M0SET endif LD_CT=#5 endif else CALL !s_LOWCT endif RETI ; Enables interrupt (INTP0) ; Input signal exists? ; Valid data exists? ; Repeat invalid time ; Repeat code invalid status ; Sets that valid data exists ; Sets leader (low) detection mode 131 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER S_LOWCT: ; Leader (low) detection mode? if(SELMOD==#0) if_bit(!P0.0) LD_CT-- if(LD_CT==#0) ; Leader (low) measuring mode SELMOD=#1 TMC0=#00000000B ; Timer: 7.81 ms CR00=#32767 TMC0=#00001100B INTM0=#00000100B CLR1 PIF0 ; Enables INTP0 interrupt CLR1 PMK0 LD_CT=#5 endif else LD_CT=#5 endif else ; Sets leader (low) detection mode CALL !S_MOSET LD_CT=#5 endif RET $EJECT ;*********************************************************** ;* Remote controller signal edge detection processing ;*********************************************************** P0_SEG CSEG INTP0: SEL RB0 CALL !WAIT switch(SELMOD) case 1: CALL break case 2: CALL break case 3: CALL break case 4: CALL break case 5: CALL ends RET1 ; Waits for 100 s !LEAD_L ; Leader low detection processing !LEAD_H ; Leader high detection processing !CDCODE ; Custom/data code loading processing !REPCD ; Repeat code detection processing !ENDCHK ; Abnormal data detection processing 132 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;**************************************** ;* Leader low detection ;**************************************** LEAD_L: if_bit(P0.0) CALL !WAIT if_bit(P0.0) CALL !CR_READ if(AX>=#3354) if(AX<#18035) SELMOD=#2 INTM0=#00000000B else CALL !S_MOSET endif else CALL !S_MOSET endif endif endif RET $EJECT ;**************************************** ;* Leader high detection ;**************************************** LEAD_H: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CALL !CR_READ if(AX>=#6710-160/2) if(AX<#20132-160/2) if(AX>#11743-160/2) SELMOD=#3 WORKP=#0000H (WORKP)+2=#8000H else SELMOD=#4 INTM0=#00000100B endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ; Level check P0.0 = 0: noise ; Waits for 100 s ; ; ; ; ; Reads timer value 6.8 ms - (1.5 ms * 4) 11.8 ms - (1.5 ms * 5) Leader high detection mode INTP0 falling edge ; Sets leader (low) detection mode ; Sets leader (low) detection mode ; Level check P0.0 = 1: noise ; Waits for 100 s ; ; ; ; ; ; ; Reads timer value 1.8 ms - 100 s * 2 - 160 clocks (edge detection timer starts) 5 ms - 100 s * 2 - 160 clocks (edge detection timer starts) Custom/data code (3 ms - 100 s * 2)? Data loading mode Initializes work area Sets most significant bit to 1 (to check end of data) ; Repeat detection mode ; INTP0 rises ; Sets leader (low) detection mode ; Sets leader (low) detection mode 133 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;****************************** ;* Custom/data code loading ;****************************** CDCODE: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CALL !CR_READ if(AX>=#1257-190/2) if(AX<#9646-190/2) if(AX>=#6710-190/2) SET1 CY else CLR1 CY endif HL=#WORKP+3 C=#4 WKSHFT: A=[HL] RORC A,1 [HL]=A HL-- DBNZ C,$WKSHFT if_bit(CY) if(WORKP+0==#CSTM) ; Level check P0.0 = 1: noise ; Waits for 100 s ; ; ; ; Reads timer value 0.5 ms - 100 s * 2 - 190 clocks (edge detection timer starts) 2.5 ms - 100 s * 2 -190 clocks (edge detection timer starts) 1.8 ms - 100 s * 2 - 190 clocks (edge detection timer starts) ; Sets work area address ; Sets number of digits of work area ; Stores 1-bit data ; Shifts 1 bit ; End of shifting all bits ; End of 32-bit input? (A) ; Custom code check A^WORKP+1 ; Custom code inverted data check if(A==#0FFH) A=WORKP+2 A^=WORKP+3 ; Data code inverted data check if(A==#0FFH) ; Stores input data RMDATA=WORKP+2 (A) ; Sets status in which input data exists SET1 CLR1 CLR1 CLR1 CALL else CALL endif else CALL endif else CALL IPDTFG RMDTSET RPT RMDTOK !S_M5SET ; Sets leader (low) detection mode !S_M0SET ; Sets leader (low) detection mode !S_M0SET !S_M0SET 134 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER endif endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ;************************************ ;* Repeat code detection ;************************************ REPCD: if_bit(P0.0) CALL !WAIT if_bit(P0.0) if_bit(RMDTOK) CALL !CR_READ if(AX<=#3354-190/2) SET1 RPT CLR1 RMDTOK CLR1 RMDTSET CALL !S_M5SET else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ; Sets leader (low) detection mode ; Sets leader (low) detection mode ; Level check P0.0 = 0: noise ; Waits for 100 s ; Valid data exists? ; Reads timer value ; 1 ms - 100 s * 2 - 190 clocks (edge detection timer starts) ; Input signal check after end of data ; Sets leader (low) detection mode ; Sets leader (low) detection mode 135 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;**************************************** ;* Abnormal data detection ;**************************************** ENDCHK: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CLR1 IPDTFG CLR1 RPT CALL !S_M0SET endif endif RET ; Level check P0.0 = 1: noise ; Waits for 100 s ; Abnormal data input ; Input signal invalid ; Sets leader (low) detection mode ;**************************************** ;* Waits for 100 s ;**************************************** WAIT: ; CALL(14), RET(12), MOV(8) B=#(838-14-12-8)/12 ; Sets 100 s WAITCT: ; 1 instruction 12 clocks DBNZ B,$WAITCT RET ;***************************************** ;* Sets leader (low) detection mode ;***************************************** S_M0SET: TMC0=#00000000B CR00=#6290 ; Sets timer to 1.5 ms TCL0=#00100000B TMC0=#00001100B ; Leader (low) detection mode SELMOD=#0 SET1 PMK0 RET ;***************************************** ;* Sets abnormal data detection mode ;***************************************** S_M5SET: ; RPTCT=#173 ; SELMOD=#5 ; RMENDCT=#3 ; TMC0=#00000000B ; CR00=#6290 TMC0=#00001100B RET ;**************************************** ;* Reads timer count value ;**************************************** CR_READ: AX=CR01 ; TMC0=#00000000B ; TMC0=#00001100B RET 250 ms measuring counter Data input end mode No-input checking counter Stops operation Sets 1.5 ms Stops operation Starts timer 136 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.3.2 Remote controller signal reception by PWM output and free running mode Table 5-2 shows the valid pulse width when a remote controller signal is received by this program. <1> through <6> below describes how each signal is processed. Table 5-2. Valid Time of Input Signal Signal Name Leader code (low) Leader code (high) Custom/data code Normal Repeat 0 1 Output Time 9 ms 4.5 ms 2.25 ms 1.125 ms 2.25 ms Valid Time 3 ms-10 ms 3 ms-5 ms 1.8 ms-3 ms 0.5 ms-1.8 ms 1.8 ms-2.5 ms <1> Leader code (low) The value of the capture/compare register 01 (CR01) is stored to memory by an interrupt request that occurs when the falling edge of INTP0 is detected. The pulse width is measured from the difference between the values of CR01 and the capture/compare register 00 (CR00) when the rising edge is generated. <2> Leader code (high) The pulse width between the high levels of the leader code is measured by the falling-edge interrupt request INTP0 and the count value of the timer. <3> Custom/data code The pulse width of each 1 bit (1 cycle) is measured by the falling-edge interrupt request INTP0. After the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide. It also checks that there is no data of the 33rd bit. <4> Repeat code detection When the high level of the leader code is less than 3 ms, the pulse width from output of the leader code to the rising edge of the INTP0 is measured. <5> Valid period of repeat code After the valid data has been input, the overflow flag (OVF0) of the 16-bit timer/event counter is tested by the main program, and the repeat code valid time of 250 ms is measured. 137 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER <6> Time out during pulse width measurement The OVF0 of the 16-bit timer/event counter is tested during pulse width measurement. If it is detected two times, time out is assumed and the data is assumed to be invalid. Because the 16-bit timer/event counter operates in the PWM mode in this example, the remote controller signal is received and, at the same time, PWM output can be performed by linking the program of 5.2 PWM Output. (1) Description of package RMDTOK : valid input signal identification flag RMDTSET : input signal identification flag OVSENS : INTP0 processing timer overflow detection flag 138 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER * Defines custom code to CSTM and declares PUBLIC 139 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use PUBLIC EXTRN EXTBIT EQU CSTM RMDATA,RPTCT,PWM,PWMOUT,TIM_PRO RPT,RMDTSET,IPDTFG,TO_FLG,OVSENS ; Custom code 9DH ; ; ; ; ; ; ; Does not use divider circuit Selects operation mode of CR00, CR01 PWM output, low active setting Selects count clock fXX PWM mode, overflow occurs INTP0 falling edge INTP0 sampling clock fXX/26 CSTM OSMS=#00000001B CRC0=#00000100B TOC0=#00000011B TCL0=#00100000B TMC0=#00000010B INTM0=#00000000B SCS=#00000011B CLR1 CLR1 CLR1 CLR1 PPR0 RPT IPDTFG RMDTSET ; INTP0 with high priority ; Clears flag ; Enables INTP0 interrupt CLR1 PMK0 EI DT_TEST: ; Detects timer overflow by INTP0 processing if_bit(OVSENS) CLR1 OVSENS CALL !TIM_PRO ; Timer overflow occurs elseif_bit(OVF0) CLR1 OVF0 SET1 TO_FLG CALL !TIM_PRO endif if_bit(RMDTSET) CLR1 RMDTSET if_bit(RPT) ; ; Repeat processing ; else ; ; Processing when input exists ; endif else if_bit(!RPT) ; ; Processing when input does not exist ; endif endif MOV PWMOUT,A CALL !PWM 140 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (3) SPD chart TIM_PRO IF: input signal exists THEN IF: valid data exists THEN IF: repeat code invalid time THEN Sets repeat code invalid status Clears RPT, IPDTFG, RMDTOK Checks timer overflow TO_CHK ELSE IF: No input exists after input of data (within 61.0 s x 2) THEN Sets that valid data exists Sets RMDTOK, RMDTSET Sets leader low detection mode S_M0SET ELSE Checks timer overflow TO_CHK TO_CHK IF: leader low detection mode THEN Sets that timer overflow does not occur ELSE Timer overflow count IF: Timer overflow occurs 2 times THEN Sets leader low detection mode S_M0SET INTP0 Selects register bank 0 Waits for 100 s WAIT CASE: SELMOD OF: 0 Leader low detection mode RM_STA OF: 1 Leader low measuring mode LEAD_L OF: 2 Leader high measuring mode LEAD_H OF: 3 Custom code/data loading mode CDCODE OF: 4 Repeat code detection mode REPCD OF: 5 Abnormal data detection mode ENDCHK 141 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER RM_STA IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Stores data of capture register to memory Selects leader low measuring mode 1 Sets INTP0 rising-edge detection mode LEAD_L IF: P00 = HIGH THEN Waits for 100 s WAIT IF: P00 = HIGH THEN Reads timer PW_CT IF: 3 ms Ieader low 10 ms THEN Selects leader high detection mode Sets INTP0 falling-edge detection mode ELSE Sets leader low detection mode S_M0SET LEAD_H THEN IF: P00 = LOW Waits for 100 s WAIT IF: P00 = LOW THEN Reads timer PW_CT IF: 2 ms leader high 5 ms THEN IF: Ieader high 3 ms THEN Selects custom code/data loading mode Initializes data storage area ELSE Selects repeat detection mode Sets INTP0 rising-edge detection mode ELSE Sets leader low detection mode S_M0SET 142 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CDCODE IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Reads timer CR_READ IF: 0.5 ms < input data 2.5 ms THEN IF: input data 1.8 ms THEN Sets CY ELSE Clears CY Stores CY to data storage area IF: end of 32 bits of data input THEN IF: custom code coincidence THEN IF: Coincidence between custom/data code and inverted data THEN Stores data code Sets input data existing status Sets IPDTFG, and clears RMDTSET, RPT, and RMDTOK Sets abrormal data detection mode S_M5SET ELSE Sets leader low detection mode S_M0SET ELSE Sets leader low detection mode S_M0SET ELSE Sets leader low detection mode S_M0SET REPCD IF: P00 = HIGH THEN Waits for 100 s WAIT IF: P00 = HIGH THEN IF: valid data exists THEN Reads timer PW_CT IF: repeat code 1 ms THEN Sets repeat code valid status Sets RPT Sets data input end status Sets abnormal data detection mode S_M5SET ELSE Sets leader low detection mode S_M0SET ELSE Sets abnormal data detection mode S_M5SET 143 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ENDCHK IF: P00 = LOW THEN Waits for 100 s WAIT IF: P00 = LOW THEN Sets input signal invalid status Clears IPDTFG, RPT Sets leader low detection mode S_M0SET PW_CT IF: OVF occurs after edge detection processing THEN IF: OVF occurs < interrupt acknowledgment processing time (65 clocks) THEN Sets that timer overflow occurs Loads capture register value Subtracts capture register value from previous value IF: borrow occurs as result of subtraction (CY = 1) THEN IF: timer overflow occurs (TO_FLG = 1) THEN Clears CY flag ELSE IF: timer overflow occurs (TO_FLG = 1) THEN Sets CY flag Stores capture register value to memory S_M0SET Selects leader low detection mode Clears TO_FLG Sets INTP0 falling-edge detection mode S_M5SET Selects abnormal data detection mode Sets repeat valid time counter 144 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC PUBLIC PUBLIC EXTRN RM_DAT DSEG RPTCT: DS RMENDCT:DS SELMOD: DS LD_CT: DS RMDATA: DS TO_CNT: DS RM_DATP DSEG CR01_NP:DS CR01_OP:DS WORKP: DS BSEG IPDTFG DBIT RMDTOK DBIT RMDTSET DBIT RPT DBIT TO_FLG DBIT OVSENS DBIT VEP0 CSEG DW AT 06H INTP0 TIM_PRO,RPT,IPDTFG,RMDTOK,RMDTSET RMENDCT,RPTCT,SELMOD,LD_CT,RMDATA TO_FLG,OVSENS CSTM SADDR 1 1 1 1 1 1 SADDRP 2 2 4 ; ; ; ; ; ; Repeat code valid time counter No-input time counter after data input Mode selection Leader signal detection counter Valid data storage area Timer overflow counter ; Newest timer counter value storage area ; Previous timer counter value storage area ; Input signal storage area ; ; ; ; ; ; Valid data exists Input signal valid Input signal exists Repeat code valid period Timer overflow occurs Detects timer overflow by INTP0 processing ; Sets vector address of INTP0 $EJECT ;****************************************************** ; Remote controller signal timer processing ;****************************************************** TM0_SEG CSEG TIM_PRO: ; Input signal exists? if_bit(IPDTFG) ; Valid data exists? if_bit(RMDTOK) RPTCT-- ; Repeat invalid time if(RPTCT==#0) ; Repeat code valid status CLR1 RPT CLR1 IPDTFG CLR1 RMDTOK endif else RMENDCT-- if(RMENDCT==#0) ; Valid data exists SET1 RMDTOK SET1 RMDTSET ; Sets leader (low) detection mode CALL !S_M0SET endif endif else ; Checks timer overflow CALL !TO_CHK endif RET 145 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER TO_CHK: if(SELMOD==#0) CLR1 TO_FLG else TO_CNT++ if(TO_CNT==#2) ; Sets start edge detection mode CALL !S_M0SET endif endif RET $EJECT ;*********************************************************** ;* Remote controller signal edge detection processing ;*********************************************************** P0_SEG CSEG INTP0: SEL RB0 CALL !WAIT ; Waits for 100 s switch(SELMOD) case 0: CALL break case 1: CALL break case 2: CALL break case 3: CALL break case 4: CALL break case 5: CALL ends RET1 !RM_STA ; Start edge detection processing !LEAD_L ; Leader low detection processing !LEAD_H ; Leader high detection processing !CDCODE ; Custom/data code loading processing !REPCD ; Repeat code detection processing !ENDCHK ; Abnormal data detection processing ;*********************************************************** ;* Start edge detection ;*********************************************************** RM_STA: ; Starts timer count CLR1 TO_FLG ; Level check P0.0 = 1: noise if_bit(!P0.0) ; Waits for 100 s CALL !WAIT if_bit(!P0.0) ; Stores capture register CR01_OP=CR01 (AX) ; Leader low detection mode SELMOD=#1 ; INTP0 rising edge INTM0=#00000100B TO_CNT=#0 endif endif RET 146 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;**************************************** ;* Leader low detection ;**************************************** LEAD_L: if_bit(P0.0) CALL !WAIT if_bit(P0.0) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX>=#12582) if(AX<#41942) SELMOD=#2 INTM0=#00000000B else CALL !S_M0SET endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ;**************************************** ;* Leader high detection ;**************************************** LEAD_H: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX>=#7549) if(AX<#20971) if(AX>#12582) SELMOD=#3 WORKP=#0000H (WORKP)+2=#8000H else SELMOD=#4 INTM0=#00000100B endif else CALL !S_M0SET endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ; Level check P0.0 = 1: noise ; Waits for 100 s ; Reads timer value ; ; ; ; 3 ms 10 ms Leader high detection mode INTP0 falling edge ; Sets start edge detection mode ; Sets start edge detection mode ; Sets start edge detection mode ; Level check P0.0 = 0: noise ; Waits for 100 s ; Reads timer value ; ; ; ; ; ; 1.8 ms 5 ms Custom/data code (3 ms)? Data loading mode Initializes work area Sets most significant bit to 1 (to confirm end of data) ; Repeat detection mode ; INTP0 rises ; Sets start edge detection mode ; Sets start edge detection mode ; Sets start edge detection mode 147 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;****************************** ;* Custom/data code loading ;****************************** CDCODE: if_bit(!P0.0) CALL !WAIT if_bit(!P0.0) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX>=#2096) if(AX<#10485) if(AX>=#7549) SET1 CY else CLR1 CY endif HL=#WORKP+3 C=#4 WKSHFT: A=[HL] RORC A,1 [HL]=A HL-- DBNZ C,$WKSHFT if_bit(CY) ; Level check P0.0 = 1: noise ; Waits for 100 s ; Reads timer value ; 0.5 ms ; 2.5 ms ; 1.8 ms ; Sets work area address ; Sets number of work area digits ; Stores 1-bit data ; Shifts 1 bit ; End of shifting all digits ; End of input of 32 bits? ; Checks custom code if(WORKP+0==#CSTM) (A) A^=WORKP+1 ; Checks custom code inverted data if(A==#0FFH) A=WORKP+2 ; Checks data code inverted data A^=WORKP+3 if(A==#0FFH) ; Stores input data RMDATA=WORKP+2 (A) ; Sets input data existing status SET1 CLR1 CLR1 CLR1 CALL else CALL endif else IPDTFG RMDTSET RPT RMDTOK !S_M5SET ; Sets start edge detection mode !S_M0SET ; Sets start edge detection mode CALL !S_M0SET endif else CALL !S_M0SET endif endif else CALL !S_M0SET endif else ; Sets start edge detection mode 148 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ;************************************ ;* Repeat code detection ;************************************ REPCD: if_bit(P0.0) CALL !WAIT if_bit(P0.0) if_bit(RMDTOK) CALL !PW_CT if_bit(!CY) TO_CNT=#0 if(AX<=#4193) SET1 RPT CLR1 RMDTOK CLR1 RMDTSET CALL !S_M5SET else CALL !S_M0SET endif else CALL !S_M0SET endif else CALL !S_M0SET endif endif endif RET $EJECT ; Sets start edge detection mode ; Sets start edge detection mode ; Level check P0.0 = 1: noise ; Waits for 100 s ; Valid data? ; Reads timer value ; 1 ms ; Checks input signal after end of data ; Sets start edge detection mode ; Sets start edge detection mode ; Sets start edge detection mode 149 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;********************************************* ;* Abnormal data detection ;********************************************* ENDCHK: ; Level check P0.0 = 1: noise if_bit(!P0.0) ; Waits for 100 s CALL !WAIT if_bit(!P0.0) ; Abnormal data input CLR1 IPDTFG ; Input signal invalid CLR1 RPT ; Sets start edge detection mode CALL !S_M0SET endif endif RET ;********************************************* ;* Calculation of capture register value ;********************************************* PW_CT: ; OVF0 after edge detection? if_bit(OVF0) ; Interrupt acknowledgment processing time = 65 clocks (MAX) if(CR01<#10000-33) (AX) CLR1 OVF0 SET1 OVSENS SET1 TO_FLG endif endif CR01_NP=CR01 (AX) A=CR01_NP+0 A-=CR01_OP X=A A=CR01_NP+1 SUBC A,CR01_OP+1 BC=AX if_bit(CY) if_bit(TO_FLG) CLR1 CY endif else if_bit(TO_FLG) SET1 CY endif endif CR01_OP=CR01_NP (AX) AX=BC CLR1 TO_FLG RET ; Loads capture register value ; AX = CR01_NP - CR01_OP ; ; ; ; Saves operation result CR01_NP > CR01_OP Timer overflow occurs (flag test) Normal data ; Timer overflow ; Error occurs ; Restores operation result 150 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER ;********************************************** ;* Waits for 100 s ;********************************************** WAIT: ; CALL (14), RET (12), MOV (8) B=#(838-14-12-8)/12 ; Sets 100 s WAITCT: ; 1 instruction 12 clocks DBNZ B,$WAITCT RET ;********************************************** ;* Sets start edge detection mode ;********************************************** S_M0SET: TO_CNT=#0 ; Start edge detection mode SELMOD=#0 ; INTP0 falling edge INTM0=#00000000B RET ;********************************************** ;* Setting of abnormal data detection mode ;********************************************** S_M5SET: ; 250 ms measuring counter RPTCT=#16 ; Data input end mode SELMOD=#5 ; No-input checking counter RMENDCT=#2 RET 151 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER 5.4 One-Shot Pulse Output The 16-bit timer/event counter has a function which outputs a one-shot pulse in synchronization with a software trigger and external trigger (INTP0/TI00/P00 pin input). When using the one-shot pulse output function, the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register (TOC0) must be set. In this section, an example for setting the one-shot pulse by using the software trigger is introduced. The OSPT flag (bit 6 of the TOC0 register) is set at arbitrary timing (such as key input). After the software trigger has occurred, TM0 is cleared and started. When the value of TM0 coincides with the value set in advance to CR01, the TO0/P30 pin output is inverted (and becomes active). When the value of TM0 later coincides with the value set in advance to CR00, the TO0/P30 pin output is inverted again (and becomes inactive). The TM0 counter is cleared and counting up is started again after the value of TM0 has coincided with the value of CR00. The output of the TO0/P30 pin, however, is not inverted even if coincidence occurs next time. TM0 is cleared and started and the output of the TO0/P30 pin is inverted only when the software trigger is set. The active level of the TO0/P30 pin is determined by selecting the initial value of the TO0/P30 pin output of the TOC0 register. Note that, when using the one-shot pulse output function with the software trigger, the OSPT flag must not be set to 1 while the one-shot pulse is output. To output the one-shot pulse again, do so after INTTM00, which is an interrupt request that occurs when TM0 coincides with CR00, has occurred. In the example presented in this section, the software trigger is designed by using key input, and "H" active output is produced 10 ms after for 1 ms. 152 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER Figure 5-16. Timing of One-Shot Pulse Output Operation by Software Trigger Count clock TM0 count value 0000 N N+1 M-2 M-1 M 0000 TO0/P30 pin output CR01 set value N CR00 set value M OSPT INTTM01 INTTM00 F_TRG 10 ms 1 ms Remark F_TRG: flag indicating that output of the one-shot pulse is in progress. For details, refer to (2) Example of use. 153 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (1) Description of package !SOP_INIT ; Sets by subroutine SOP_INIT 154 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use Because bit 6 (OSPT) of the 16-bit timer output control register (TOC0) is not set again while the pulse is output in the example of this package, the F_TRG flag is set as soon as the OSPT flag has been set as shown in Figure 5-16. Even if the next output request is issued while the F_TRG flag is set (i.e., while the pulse is output), the OSPT flag is not set. After the one-shot pulse has been output (INTTM00 occurs), clear the F_TRG flag. EXTRN SOP_INT M1PR0 CSEG RES_STA: OSMS=#00000001B CLR1 P3.0 CLR1 PM3.0 CALL !SOP_INIT * * if(key request issued) if_bit(!F_TRG) SET1 OSPT SET1 F_TRG endif endif if_bit(TMIF00) CLR1 F_TRG CLR1 TMIF00 endif * * ; ; ; ; Does not use divider circuit Sets 0 to output latch if multiplexed pin is used Sets output mode if multiplexed pin is used One-shot pulse output initial setting routine ; Previous output ends? ; Clears and starts 16-bit counter ; Sets one-shot pulse trigger flag ; ; ; End of one-shot pulse output? ; Clears one-shot trigger flag ; Clears TMIF00 request flag ; (3) SPD chart SOP_INIT Stops timer operation Selects count clock of 16-bit timer register Uses CR00 and CR01 as compare registers Sets compare register 00 (CR00) (Time required from start of trigger to second inversion of TO0 output) Sets compare register 01 (CR01) (Time required from start of trigger to first inversion of TO0 output) Selects one-shot pulse output mode Starts on coincidence between TM0 and CR00 (enables timer operation) 155 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC SOP_INIT OPINIT CSEG SOP_INIT: TMC0=#00000000B TCL0=#01000000B CRC0=#00000000B CR00=#11550-1 CR01=#10500-1 TOC0=#00110111B TMC0=#00001100B RET END ; ; ; ; ; ; ; ; Stops timer operation Count clock of 16-bit timer register: 1.05 MHz Uses CR00 and CR01 as compare registers Sets compare register to 11 ms Sets compare register to 10 ms Selects one-shot pulse mode Starts on coincidence between TM0 and CR00 (enables timer operation) 5.5 PPG Output When using the 16-bit timer/event counter in the PPG (Programmable Pulse Generator) mode, the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register (TOC0) must be set. As the PPG output pulse, a square wave with a cycle specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00) and a pulse width specified by the count value set in advance to the 16-bit capture/ compare register 01 (CR01) is output from the TO0/P30 pin. In the application example shown in this section, the output waveform is changed by using the PPG output. Data indicating the one cycle and pulse width of the output waveform is stored in ROM. This data is stored in the compare register. The cycle and pulse width of the PPG output in this program can be changed in units of 1 ms to 10 ms. Therefore, the cycle can be set in a range of 2 to 10 ms, and the pulse width can be set in a range of 1 to 9 ms. If the cycle is equal to or less than the pulse width when the output waveform is changed, the data is not changed. The output waveform is changed after the end of one output cycle. Figure 5-17 shows the PPG output waveform changing timing. Figure 5-17. PPG Output Waveform Changing Timing Request for change Data changed Request for change Data changed Pulse width 1 cycle 156 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (1) Description of package * Input parameter of SPG_INIT routine * Input/output parameters of SPG_INIT routine and INTTM00 interrupt PARUSUP : Pulse width time change data storage area SAIKURUP : 1-cycle time change data storage area 157 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER !PPG_INIT ; Sets by subroutine PPG_INIT 158 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (2) Example of use EXTRN EXTRN EXTRN EXTRN ; SMIN PMIN SPG_INIT SAIKURUP.PARUSUP SAIKURU,PARUSU PDAT,SDAT EQU EQU 02H 01H ; Minimum cycle time ; Minimum pulse width time * * ; Does not use divider circuit OSMS=#00000001B ; Sets initial cycle value SAIKURU=#SMIN ; Sets initial pulse width value PARUSU=#PMIN ; Clears output latch to 0 if multiplexed pin is used CLR1 P3.0 ; Sets output mode if multiplexed pin is used CLR1 PM3.0 ; CALL !SPG_INIT ; EI * * if(request for changing square wave) ; If SAIKURUP > PARUSU if(SAIKURU > PARUSU) (A) ; Data 1 address XXX0 A=PARUSU ; Data 2 address XXX2 A-- ; Data 3 address XXX4 A <<= 1 ; * X=A ; Table reference of low-order 8 bits of value stored to A=#0 ; compare register AX+=#PDAT ; X register low-order 8 bits HL=AX ; X=[HL] (A) ; Table reference of high-order 8 bits of value stored to compare register HL++ ; A register high-order 8 bits A=[HL] ; PARUSUP=AX ; A=SAIKURU A-- A-- A <<= 1 X=A A=#0 AX+=#SDAT HL=AX X=[HL] (A) HL++ A=[HL] SAIKURUP=AX CLR1 TMIF00 CLR1 TMMK00 endif endif * * ; ; Cycle time storage processing ; ; ; ; ; ; ; ; ; ; ; ; Clears request flag ; Enables compare register 00 interrupt ; No data change ; 159 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (3) SPD chart PPG_INIT Stops timer operation Selects count clock of 16-bit timer register Uses CR00 and CR01 as compare registers Table reference of compare data corresponding to PARUSU area contents and stores it in PARUSU area Table reference of compare data corresponding to SAIKURU area contents and stores it in SAIKURUP area Stores contents of SAIKURUP area to compare register 00 (CR00) Stores contents of PARUSUP area to compare register 01 (CR01) Sets successive pulse output and sets initial value "H" of TO0 pin output Starts on coincidence between TM0 and CR00 (enables timer operation) INTTM00 Selects register bank 2 Stores contents of SAIKURUP area to compare register 00 (CR00) Stores contents of PARUSUP area to compare register 01 (CR01) Disables INTTM00 interrupt 160 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC SPG_INIT,PDAT,SDAT PUBLIC SAIKURU,PARUSU EXTRN SAIKURUP,PARUSUP ; ;************************************************ ; RAM definition ;************************************************ ; PPGRAM DSEG SADDR ; 1 cycle time storage area SAIKURU: DS 1 ; Pulse width storage area PARUSU: DS 1 ; ;************************************************ ; PPG output initial setting ;************************************************ PPGINIT CSEG SPG_INIT: ; Stops timer operation TMC0=#00000000B ; Count clock of 16-bit timer register: 4.19 MHz TCL0=#00100000B ; Uses CR00 and CR01 as compare register CRC0=#00000000B ; Data 1 address XXX0 A=PARUSU ; Data 2 address XXX2 A-- ; Data 3 address XXX4 A <<= 1 ; * X=A ; Table reference of low-order 8 bits of value stored to A=#0 ; compare register AX+=#PDAT ; X register low-order 8 bits HL=AX ; X=[HL] (A) ; Table reference of high-order 8 bits of value stored to compare register HL++ ; A register high-order 8 bits A=[HL] ; PARUSUP=AX ; ; ; Cycle time storage processing A=SAIKURU ; A-- ; A-- ; A <<= 1 ; X=A ; A=#0 ; AX+=#SDAT ; HL=AX ; X=[HL] (A) ; HL++ ; A=[HL] ; SAIKURUP=AX ; Sets compare register to 2 ms CR00=SAIKURUP (AX) ; Sets compare register to 1 ms CR01=PARUSUP (AX) ; Sets successive pulse output and initial value `H' TOC0=#00011011B ; Starts on coincidence between TM0 and CR00 (enables timer operaTMC0=#00001100B tion) RET ; 161 CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER PDAT: DW DW DW DW DW DW DW DW DW SDAT: DW DW DW DW DW DW DW DW DW END 4201 8403 12605 16807 21009 25211 29413 33615 37817 8403 12605 16807 21009 25211 29413 33615 37817 42019 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Address XXX0 Address XXX2 Address XXX4 Address XXX0 Address XXX2 Address XXX4 PUBLIC ; VETM00 PARUSUP,SAIKURUP CSEG DW AT 20H INTTM00 ; P2RAM DSEG SADDRP ; Pulse width time changing data storage area PARUSUP: DS 2 ; 1 cycle time changing data storage area SAIKURUP: DS 2 ;**************************************************************** ; PPG output (cycle pulse width time changing interrupt) ;**************************************************************** ; TM00 CSEG ; INTTM00: ; Selects bank 2 SEL RB2 ; CR00, CR01 stores pulse width and cycle time changing data CR01=PARUSUP (AX) ; CR00=SAIKURUP (AX) ; Disables compare register 00 interrupt SET1 TMMK00 ; RETI END 162 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER The 8-bit timer/event counter of the 78K/0 series has three functions: interval timer, external event counter, and square wave output. Two channels of 8-bit timers/event counters are provided and these timers/event counters can be used as a 16-bit timer/event counter when connected in cascade. The 8-bit timers/event counters are set by the following registers: * Timer clock select register 1 (TCL1) * 8-bit timer mode control register (TMC1) * 8-bit timer output control register (TOC1) * Port mode register 3 (PM3) * Port 3 (P3) 163 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-1. Format of Timer Clock Select Register 1 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol 7 6 5 4 3 2 1 0 Address FF41H At reset 00H R/W R/W TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 TCL13 TCL12 TCL11 TCL10 Selects count clock of 8-bit timer register 1 MCS = 1 MCS = 0 0 0 0 0 1 1 1 1 1 1 1 1 Others 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Falling edge of TI1 Rising edge of TI1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Setting prohibited fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/212 (1.2 kHz) TCL17 TCL16 TCL15 TCL14 Selects count clock of 8-bit timer register 2 MCS = 1 MCS = 0 0 0 0 0 1 1 1 1 1 1 1 1 Others 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Falling edge of TI2 Rising edge of TI2 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Setting prohibited fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/212 (1.2 kHz) Caution Before writing new data to TCL1, stop the timer operation once. 164 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Remarks 1. fXX 2. fX : main system clock frequency (fX or fX/2) : main system clock oscillation frequency 3. TI1 : input pin of 8-bit timer register 1 4. TI2 : input pin of 8-bit timer register 2 5. MCS: bit 0 of oscillation mode select register (OSMS) 6. ( ) : at fX = 5.0 MHz 165 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-2. Format of Timer Clock Select Register 1 (PD78098, 78098B subseries) Symbol 7 6 5 4 3 2 1 0 Address FF41H At reset 00H R/W R/W TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 TCL13 TCL12 TCL11 TCL10 0 0 0 0 1 1 1 1 1 1 1 1 Others 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Selects count clock of 8-bit timer register 1 Falling edge of TI1 Rising edge of TI1 fXX/2 (2.0 MHz) fXX/22 (1.0 MHz) fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) fXX/29 (7.8 kHz) fXX/211 (2.0 kHz) Setting prohibited TCL17 TCL16 TCL15 TCL14 0 0 0 0 1 1 1 1 1 1 1 1 Others 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Selects count clock of 8-bit timer register 2 Falling edge of TI2 Rising edge of TI2 fXX/2 (2.0 MHz) fXX/22 (1.0 MHz) fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) fXX/29 (7.8 kHz) fXX/211 (2.0 kHz) Setting prohibited Caution Before writing new data to TCL1, stop the timer operation once. Remarks 1. fXX : main system clock frequency 2. TI1: input pin of 8-bit timer register 1 3. TI2: input pin of 8-bit timer register 2 4. ( ) : at fXX = 4.0 MHz 166 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-3. Format of Timer Clock Select Register 1 (PD780018, 780018Y subseries) Symbol 7 6 5 4 3 2 1 0 Address FF41H At reset 00H R/W R/W TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 TCL13 TCL12 TCL11 TCL10 0 0 0 0 1 1 1 1 1 1 1 1 Others 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Selects count clock of 8-bit timer register 1 Falling edge of TI1 Rising edge of TI1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Setting prohibited fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) TCL17 TCL16 TCL15 TCL14 0 0 0 0 1 1 1 1 1 1 1 1 Others 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Selects count clock of 8-bit timer register 2 Falling edge of TI2 Rising edge of TI2 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 Setting prohibited fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) Caution Before writing new data to TCL1, stop the timer operation once. Remarks 1. fXX : main system clock frequency (fX) 2. fX : main system clock oscillation frequency 3. TI1 : input pin of 8-bit timer register 1 4. TI2 : input pin of 8-bit timer register 2 5. ( ) : at fX = 5.0 MHz 167 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-4. Format of 8-Bit Timer Mode Control Register Symbol TMC1 7 0 6 0 5 0 4 0 3 0 2 1 0 TCE1 Address FF49H At reset 00H R/W R/W TMC12 TCE2 TCE1 0 1 Controls operation of 8-bit timer register 1 Stops operation (clears TM1 to 0) Enables operation TCE2 0 1 Controls operation of 8-bit timer register 2 Stops operation (clears TM2 to 0) Enables operation TMC12 Selects operation mode 0 1 8-bit timer register x 2 channel mode (TM1, TM2) 16-bit timer register x 1 channel mode (TMS) Cautions 1. Before changing the operation mode, stop the timer operation. 2. When using the two 8-bit timer registers as a one 16-bit timer register, enable or stop the operation by using TCE1. 168 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-5. Format of 8-Bit Timer Output Control Register Symbol TOC1 7 LVS2 6 5 4 3 LVS1 2 1 0 Address FF4FH At reset 00H R/W R/W LVR2 TOC15 TOE2 LVR1 TOC11 TOE1 TOE1 0 1 Controls output of 8-bit timer/event counter 1 Disables output (port mode) Enables output TOC11 Controls timer output F/F of 8-bit timer/event counter 1 0 1 Disables reverse operation Enables reverse operation LVS1 0 0 1 1 LVR1 0 1 0 1 Sets status of timer output F/F of 8-bit timer/ event counter 1 Not affected Resets timer output F/F (to 0) Sets timer output F/F (to 1) Setting prohibited TOE2 0 1 Controls output of 8-bit timer/event counter 2 Disables output (port mode) Enables output TOC15 Controls timer output F/F of 8-bit timer/event counter 2 0 1 Disables reverse operation Enables reverse operation LVS2 0 0 1 1 LVR2 0 1 0 1 Sets status of timer output F/F of 8-bit timer/ event counter 2 Not affected Resets timer output F/F (to 0) Sets timer output F/F (to 1) Setting prohibited Cautions 1. Before setting TOC1, be sure to stop the timer operation. 2. LVS1, LVS2, LVR1, and LVR2 are always 0 when they are read. 169 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER Figure 6-6. Format of Port Mode Register 3 Symbol PM3 7 6 5 PM35 4 PM34 3 PM33 2 PM32 1 0 Address FF23H At reset FFH R/W R/W PM37 PM36 PM31 PM30 PM3n 0 1 Selects input/output mode of P3n pin (n = 0-7) Output mode (output buffer ON) Input mode (output buffer OFF) 170 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.1 Setting of Interval Timer When using an 8-bit timer/event counter as an interval timer, set an operation mode by the 8-bit timer mode control register (TMC1) and interval time by the timer clock select register 1 (TCL1). After that, set the values of the compare registers (CR10 and CR20) from the setup time and count clock. The setup time is determined by using the following expression: Setup time = (Compare register value + 1) x Count clock cycle The setup time can be calculated in the same manner regardless of whether each 8-bit timer/event counter is used or two 8-bit timers/event counters are used as a 16-bit timer/event counter. The count clock when two 8-bit timers/ event counters are used as a 16-bit timer/event counter, however, is selected by the bits 0 through 3 (TCL10 through TCL13) of TCL1. Examples of the modes of the 8-bit timers and 16-bit timer are described next. Figure 6-7. Count timing of 8-Bit Timers Count clock TM1, TM2 N-2 N-1 N 00 01 02 N-2 N-1 N INTTM1, INTTM2 TO1 171 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.1.1 Setting of 8-bit timers In this example, 8-bit timer 2 is used to set two types of interval times: 500 s and 100 ms. (a) To set interval of 500 s <1> Setting of TMC1 Select the 8-bit timer register x 2 channel mode and enables the operation of the 8-bit timer 2. <2> Setting of TCL1 Select fXX/24 that allows setting of 500 s or more and has the highest resolution (OSMS = 01H). <3> Setting of CR20 500 s = (N + 1) x 1 4.19 MHz/24 * N = 500 s x 4.19 MHz/24 - 1 = * 130 (1) Program list OSMS = #00000001B ; Does not use divider circuit TCL1 = #10011001B CR20 = #130 TMC1 = #00000010B (b) To set interval of 100 ms <1> Setting of TMC1 Select the 8-bit timer register x 2 channel mode and enables the operation of the 8-bit timer 2. <2> Setting of TCL1 Select fXX/211 that allows setting of 100 ms or more and has the highest resolution (OSMS = 01H). <3> Setting of CR20 100 ms = (N + 1) x 1 4.19 MHz/211 ; Selects fXX/24 as count clock N = 100 ms x 4.19 MHz/211 - 1 *=* 204 (1) Program list OSMS = #00000001B ; Does not use divider circuit TCL1 = #11111111B CR20 = #204 TMC1 = #00000010B ; Selects fXX/211 as count clock 172 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.1.2 Setting of 16-bit timer In this example, 8-bit timers 1 and 2 are connected in cascade as a 16-bit timer to set two types of interval times: 500 ms and 10 s. (a) To set interval of 500 ms <1> Setting of TMC1 Select the 16-bit timer register x 1 channel mode and enables the operation of the 8-bit timers 1 and 2. <2> Setting of TCL1 Select fXX/25 that allows setting of 500 ms or more and has the highest resolution (OSMS = 01H). <3> Setting of CR10 and CR20 500 ms = N+1 4.19 MHz/25 * N = 500 ms x 4.19 MHz/25 - 1 = * 65468 = FF6CH CR10 = 6CH, CR20 = FFH (1) Program list OSMS = #00000001B ; Does not use divider circuit TCL1 = #00001010B CR10 = #06CH CR20 = #0FFH ; Sets 65468 to CR10 and CR20 ; CR10 = 6CH, CR20 = FFH TMC1 = #00000111B (b) To set interval of 10 s <1> Setting of TMC1 Select the 16-bit timer register x 1 channel mode and enable the operation of the 8-bit timers 1 and 2. <2> Setting of TCL1 Select fXX/211 that allows setting of 10 s or more and has the highest resolution (OSMS = 01H). <3> Setting of CR10 and CR20 10 s = N+1 4.19 MHz/211 N = 10 s x 4.19 MHz/211 - 1 *=* 20458 = 4FEAH CR10 = EAH, CR20 = 4FH (1) Program list OSMS = #00000001B ; Does not use divider circuit TCL1 = #00001111B CR10 = #0EAH CR20 = #4FH TMC1 = #00000111B ; Sets 20458 to CR10 and CR20 ; CR10 = EAH, CR20 = 4FH 173 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER 6.2 Musical Scale Generation This section shows an example of a program that uses the square wave output (P31/TO1) of an 8-bit timer/event counter and generates a musical scale by supplying pulses to an external buzzer. Figure 6-8. Musical Scale Generation Circuit VDD PD78054 P31/TO1 The output frequency of the P31/TO1 pin is set by the count clock and a compare register. In this example, the central frequency of the musical scale is set to a range of 523 to 1046 Hz. Therefore, fXX/25 is selected as the count clock (oscillation mode select register: OSMS = 01H). Table 6-1 shows the musical scale, the set value of the compare register, and frequency of the output pulse. Because one cycle of the timer output is created when the value of the timer coincides with the value of the compare register two times, the interval time is set as half a cycle time. Figure 6-9. Timer Output and Interval Interval CR10 coincidence interval Timer output cycle 174 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER As for the time length of a sound, the output time is determined by setting an interval time with 8-bit timer/event counter 2 and by counting the number of times the interrupt generated by the timer/event counter. In this example, 8-bit timer/event counter 2 is set to 20 ms. Table 6-1. Musical Scale and Frequency Musical Scale Do Re Mi Fa So La Tee Do Musical Scale Frequency Hz 523.25 587.33 659.25 698.46 783.98 880.00 987.77 1046.5 Compare Register Value 124 111 98 93 83 73 65 62 Output Frequency Hz 524.3 585.1 662.0 697.2 780.2 885.6 993.0 1040 The format of the data table for this program is shown below. TABLE: DB musical scale data 1, sound length data 1 DB musical scale data 2, sound length data 2 . . . . . . DB musical scale data n, sound length data n DB 0, 0 The musical scale data is set to 0 for rest, and the sound length data is set to 0 for the end of data. Example Number of counts of 8-bit timer/event counter to output sound for 1 second Number of counts = 1 s/20 ms = 50 (50 is set as number of counts) This program sequentially outputs do, re, mi, and so on, for 1 second each. 175 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER (1) Description of package * 8-bit timer/event counters 1 and 2 * P31/TO1 * Sets by subroutine MLDY * Enables interrupt * Call subroutine MLDY (2) Example of use EXTRN MLDY . . . CALL EI !MLDY 176 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER (3) SPD chart MLDY Sets P31/TO1 in output mode Clears pointer (POINT) of reference table to 0 Sets initial data 1 as sound length data (LNG) Sets 8-bit timer/event counter 1 in output mode Sets 8-bit timer/event counter 2 to 20 ms Enables 8-bit timer 2 interrupt INTTM2 Selects register bank 0 Decrements sound length data (LNG) IF: end of output time THEN References sound data indicated by pointer IF: sound data mute data THEN Sets sound data to compare register of timer 1 ELSE Disables TO1 output of timer 1 References sound length data IF: sound length data musical scale generation end data THEN Sets sound length data ELSE Disables timer 2 interrupt Stops timer 2 operation 177 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER (4) Program list PUBLIC MLDY VETM2 CSEG DW AT 26H INTTM2 SADDR 1 1 ; Sets vector address of 8-bit timer/event counter ML_DAT DSEG POINT: DS LNG: DS ; Pointer for table data ; Sound length data ;************************************************* ;* Musical scale generation initialize ;************************************************* ML_SEG CSEG MLDY: ; CLR PM3.1 ; POINT=#0 LGN=#1 ; OSMS=#00000001B ; TOC1=#00000011B TCL1=#11101010B ; CR20=#163 ; TMC1=#00000010B ; CLR1 TMMK2 RET $EJECT Sets P3.1 in output mode Initial setting of pointer Does not use divider circuit Sets TO1 output mode Sets timer 2 to 20 ms Enables timer 2 operation Enables timer 2 interrupt 178 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER ;*********************************************** ; Sets musical scale generation data ;*********************************************** TM2_SEG CSEG INTTM2: SEL RB0 LNG-- if(LNG==#0) B=POINT (A) ; Sets table first address HL=#TABLE A=[HL+B] if(A!=#0) ; Sets sound data CLR1 TCE1 CR10=A SET1 TOE1 SET1 TCE1 else CLR1 TOE1 endif ; B++ ; A=[HL+B] ; if(A!=#0) ; LNG=A B++ POINT=B (A) else ; SET1 TMMK2 ; CLR1 TCE2 endif endif RETI ;*********************************************** ; Musical scale data table ;*********************************************** TABLE: ; DB 124,50 ; DB 111,50 ; DB 98,50 ; DB 93,50 ; DB 83,50 ; DB 73,50 ; DB 65,50 ; DB 62,50 ; DB 00,00 Increments pointer Loads sound length data Sound output in progress? Sets sound length data Disables timer 2 interrupt Stops timer 2 operation Do Re Mi Fa So La Tee Do End 179 [MEMO] 180 CHAPTER 7 APPLICATIONS OF WATCH TIMER The watch timer of the 78K/0 series has a watch timer function that causes the timer to overflow every 0.5 second by using the main system clock or subsystem clock as the clock source, and an interval timer function that allows you to set six types of reference times. These two functions can be simultaneously used. The watch timer is set by using timer clock select register 2 (TCL2) and watch timer mode control register (TMC2). 181 CHAPTER 7 APPLICATIONS OF WATCH TIMER Figure 7-1. Format of Timer Clock Select Register 2 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol 7 6 5 4 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Selects count clock of watchdog timer MCS = 1 MCS = 0 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) (1.2 kHz) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (2.4 kHz) fX/210 fX/212 fX/211 TCL24 Selects count clock of watch timer MCS = 1 MCS = 0 fX/28 (19.5 kHz) 0 1 fXX/27 fXT (32.768 kHz) fX/27 (39.1 kHz) TCL27 TCL26 TCL25 Selects frequency of buzzer output MCS = 1 MCS = 0 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 fXX/210 fXX/211 Setting prohibited fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) fX/212 (1.2 kHz) Caution Before writing new data to TCL2, stop the timer operation once. Remarks 1. fXX 2. fX 3. fXT 4. x : main system clock frequency (fX or fX/2) : main system clock oscillation frequency : subsystem clock oscillation frequency : don't care 5. MCS: bit 0 of oscillation mode select register (OSMS) 6. ( ) : at fX = 5.0 MHz or fXT = 32.768 kHz 182 CHAPTER 7 APPLICATIONS OF WATCH TIMER Figure 7-2. Format of Timer Clock Select Register 2 (PD78098, 78098B subseries) Symbol 7 6 5 4 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) fXX/29 (7.8 kHz) fXX/211 (2.0 kHz) Selects count clock of watchdog timer TCL24 0 1 fXX/27 (31.3 kHz) fXT (32.768 kHz) Selects count clock of watch timer TCL27 TCL26 TCL25 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 (7.8 kHz) fXX/210 (3.9 kHz) fXX/211 (1.95 kHz) Setting prohibited Selects frequency of buzzer output Caution Before writing new data to TCL2, stop the timer operation once. Remarks 1. fXX: main system clock frequency 2. fXT: subsystem clock oscillation frequency 3. x : don't care 4. ( ): at fXX = 4.0 MHz or fXT = 32.768 kHz 183 CHAPTER 7 APPLICATIONS OF WATCH TIMER Figure 7-3. Format of Timer Clock Select Register 2 (PD780018, 780018Y subseries) Symbol 7 6 5 4 3 0 2 1 0 Address FF42H At reset 00H R/W R/W TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211 TCL22 TCL21 TCL20 Selects count clock of watchdog timer fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/211 (2.4 kHz) TCL24 0 1 fXX/27 fXT Selects count clock of watch timer fX/27 (39.1 kHz) TCL27 TCL26 TCL25 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Disables buzzer output fXX/29 fXX/210 fXX/211 Setting prohibited Selects frequency of buzzer output fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/211 (2.4 kHz) Caution Before writing new data to TCL2, stop the timer operation once. Remarks 1. fXX: main system clock frequency (fX) 2. fX : main system clock oscillation frequency 3. fXT: subsystem clock oscillation frequency 4. x : don't care 5. ( ): at fX = 5.0 MHz or fXT = 32.768 kHz 184 CHAPTER 7 APPLICATIONS OF WATCH TIMER Figure 7-4. Format of Watch Timer Mode Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol TMC2 7 0 TMC20 0 1 6 5 4 3 2 1 0 Address FF4AH At reset 00H R/W R/W TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Selects watch operation mode Normal operation mode (sets flag at fW/214) Fast-forward mode (sets flag at fW/25) TMC21 0 1 Clears after operation stopped Enables operation Controls operation of prescaler TMC22 0 1 Clears after operation stopped Enables operation Controls operation of 5-bit counter TMC23 At fXX = 5.0 MHz 0 1 214/fW 213/fW (0.4 sec) (0.2 sec) Selects set time of watch timer At fXX = 4.19 MHz 214/fW 213/fW (0.5 sec) (0.25 sec) 214/fW 213/fW At fXT = 32.768 kHz (0.5 sec) (0.25 sec) TMC26 TMC25 TMC24 At fXX = 5.0 MHz 0 0 0 0 1 1 Others 0 0 1 1 0 0 0 1 0 1 0 1 24/fW 25/fW 26/fW 27/fW 28/fW 29/fW (410 s) (819 s) (1.64 ms) (3.28 ms) (6.55 ms) (13.1 ms) Selects interval time of prescaler At fXX = 4.19 MHz 24/fW 25/fW 26/fW 27/fW 28/fW 29/fW (488 s) (977 s) (1.95 ms) (3.91 ms) (7.81 ms) (15.6 ms) At fXT = 32.768 kHz 24/fW 25/fW 26/fW 27/fW 28/fW 29/fW (488 s) (977 s) (1.95 ms) (3.91 ms) (7.81 ms) (15.6 ms) Setting prohibited Caution Do not often clear the prescaler when the watch timer is used. Remarks 1. fW : watch timer clock frequency (fXX/27 or fXT) 2. fXX: main system clock frequency (fX or fX/2) 3. fX : main system clock oscillation frequency 4. fXT: subsystem clock oscillation frequency 185 CHAPTER 7 APPLICATIONS OF WATCH TIMER Figure 7-5. Format of Watch Timer Mode Control Register (PD78098, 78098B subseries) Symbol TMC2 7 0 6 5 4 3 2 1 0 Address FF4AH At reset 00H R/W R/W TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 TMC23 TMC20 Selects set time of watch flag 0 1 0 1 1 0 214/fW (0.5s) 213/fW (0.25s) 25/fW (977 s) 24/fW (488 s) TMC21 Controls operation of prescaler 0 1 Clears after operation stopped Enables operation TMC22 Controls operation of 5-bit counter 0 1 Clears after operation stopped Enables operation TMC26 TMC25 TMC24 Selects interval time of prescaler 0 0 0 0 1 1 Others 0 0 1 1 0 0 0 1 0 1 0 1 24/fW (488 s) 2 /fW (977 s) 5 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) Setting prohibited Caution Do not often clear the prescaler when the watch timer is used. Remarks 1. fW : watch timer clock frequency (fX/28 or fXT) 2. ( ): at fW = 32.768 kHz 186 CHAPTER 7 APPLICATIONS OF WATCH TIMER 7.1 Watch and LED Display Program As an example of using the watch timer, this section introduces a program that counts time by using an 0.5 second overflow and dynamically displays LED at intervals of 1.95 ms. To count time, an overflow flag is tested each time a subroutine is called. When the flag is set, time is counted up in seconds. Because an overflow occurs every 0.5 second, it takes 1 minute to count 120 times. The overflow flag is tested at intervals of 1.95 ms so that the flag is tested without fail. The watch of this program is 24-hour watch. The high-order and low-order digits of minute and hour data are stored in separate areas of memory. Figure 7-6. Concept of Watch Data Second data 0-120 Minute data Hour data Low-order High-order Low-order High-order digit 0-9 digit 0-5 digit 0-9 digit 0-2 187 CHAPTER 7 APPLICATIONS OF WATCH TIMER As LED dynamic display, four digits are displayed with the display digit changed at intervals of 1.95 ms. In this example, the high-order 4 bits of P3 are used as a digit signal, and P5 that can directly drive an LED is selected as a segment signal. The digit of an LED specified by a display digit area (DIGCT) in an LED display area is displayed. To change the digit signal, the segment signal is turned off so that the adjacent digits are not displayed. Figure 7-7. LED Display Timing P34 P35 P36 P37 Port 5 DIGIT 0 1 2 3 0 1 2 3 0 1 2 3 Segment signal OFF Figure 7-8. Circuit Example of Watch Timer PD78054 7-segment LED x 4 P50 P57 P37 P36 P35 P34 188 CHAPTER 7 APPLICATIONS OF WATCH TIMER (1) Description of package HOURDP : hour data storage area * Watch timer * P34-37 * P5 * TMC2 = #00100110B ; 0.5-second watch operation at 1.95 ms interval * TMMK3 = 0 ; enables watch timer interrupt 189 CHAPTER 7 APPLICATIONS OF WATCH TIMER (3) SPD chart INTTM3 Selects register bank 0 Watch count TIME LED display LEDDSP LEDDSP Turns OFF segment signal IF: digit counter (DIGCT) = 0 THEN Initial setting of digit signal ELSE Shifts digit signal I bit higher Outputs segment signal of digit indicated by digit counter Increments digit counter TIME IF: Sets watch timer interrupt request flag THEN Increments second counter IF: second counter = 120 THEN Sets second counter to 0 Increments minute (low) counter IF: minute (low) counter = 10 THEN Clears minute (low) counter to 0 Increments minute (high) counter IF: minute (high) counter = 6 THEN Clears minute (high) counter to 0 Increments hour (low) counter IF: hour data 0204H THEN IF: hour (low) counter = 10 THEN Clears hour (low) counter to 0 Increments hour (high) counter ELSE Clears hour counter to 0 190 CHAPTER 7 APPLICATIONS OF WATCH TIMER (4) Program list PUBLIC HOURDP,MINDP,SECD,LEDDP WT_DATP DSEG MINDP: DS HOURDP: DS SECD: DS DIGCT: DS LEDDP: DS VETM3 CSEG DW SADDRP 2 2 1 1 4 AT 1EH INTTM3 ; ; ; ; ; Minute data storage area Hour data storage area Second data storage area LED display digit area LED display area ; Sets vector address of watch timer ;*************************************** ;* Interval interrupt processing ;*************************************** TM3_SEG CSEG INTTM3: SEL RB0 CALL !TIME CALL !LEDDPSP RETI 191 CHAPTER 7 APPLICATIONS OF WATCH TIMER ;************************************ ; LED display ;************************************ LEDDPSP: P5=#0FFH DIGCT&=#00000011B if(DIGCT==#0) A=P3 A&=#00001111B A|=#00010000B P3=A else A=P3 A&=#11110000B X=A A=P3 A+=X P3=A endif B=DIGCT (A) HL=#LEDDP B=[HL+B] (A) HL=#SEGDT P5=[HL+B] (A) DIGCT++ RET SEGDT: DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB $EJECT 11000000B 11111001B 10100100B 10110000B 10011001B 10010010B 10000010B 11111000B 10000000B 10010000B 10001000B 10000011B 11000110B 10100001B 10000110B 10001110B ; Turns OFF segment output ; Adjusts digit counter (0-3) ; Initial setting of digit signal (high-order 4 bits) ; Shifts high-order 4 bits ; ; ; ; ; Sets address of display data Display area first address Sets display data Conversion to segment data Outputs segment signal ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 0 1 2 3 4 5 6 7 8 9 A B C D E F 192 CHAPTER 7 APPLICATIONS OF WATCH TIMER ;******************************** ;* Watch count up ;******************************** TIME: if_bit(WTIF) CLR1 WTIF SECD++ if(SECD==#120) SECD=#0 (MINDP+0)++ if((MINDP+0)==#10) (MINDP+0)=#0 (MINDP+1)++ if(MINDP+1==#6) (MINDP+1)=#0 (HOURDP+0)++ if(HOURDP!=#0204H) (AX) if((HOURDP+0)==#10) (HOURDP+0)=#0 (HOURDP+1)++ endif else HOURDP=#0000H endif endif endif endif endif RET ; 0.5 second test ; 120 = 60 seconds/0.5 ; Increments minute (low) ; Carry occurs ; Increments minute (high) ; Carry occurs ; Hour data 24? ; Carry occurs 193 [MEMO] 194 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE The 78K/0 series is provided with the serial interface shown in Table 8-1. Table 8-1. Serial Interface Channel of Each Subseries Configuration of Serial Interface Channel 0 3-wire 2-wire SBI I2C bus Channel 1 3-wire Channel 2 UART Channel 3 Channel 4 Channel 5 3-wire 3-wire with timedivision function I 2C bus (multimaster supporting) Subseries 3-wire 3-wire with automatic transmission/ reception function PD78054 PD78054Y PD78064 PD78064Y PD78078 PD78078Y PD78083 PD78098 PD780018 PD780018Y PD780058 PD780058Y PD780308 PD780308Y PD78058F PD78058FY PD78064B PD78070A PD78070AY PD78075B PD78075BY PD78098B x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Note Note x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Note Note x x x x x x x x x x x x x Note With time-division transfer function Remark : Function provided, x: Function not provided 195 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE The serial interface of the 78K/0 series has a different function depending on the subseries, as shown in Table 8-1. This chapter explains each function and application example of the serial interface. The function supported by each subseries are listed in Table 8-2. For details of application examples of using the serial interface function of a specific subseries, refer to the section or paragraph marked in this table. Table 8-2. Items Supported by Each Subseries Item 8.1.1 Communication in 2-wire serial I/O mode 8.1.2 Communication in I2C bus mode 8.2 Interface with OSD LSI (PD6451A) 8.3 Interface in SBI Mode 8.4 8.5 Interface in Interface in 3-Wire Serial I/O Asynchronous Mode Serial Interface (UART) Mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Subseries PD78054 PD78054Y PD78064 PD78064Y PD78078 PD78078Y PD78083 PD78098 PD780018 PD780018Y PD780058 PD780058Y PD780308 PD780308Y PD78058F PD78058FY PD78064B PD78070A PD78070AY PD78075B PD78075BY PD78098B 196 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE The functions and operations of the serial interface are specified by using the following registers: Table 8-3. Registers of Serial Interface Serial Interface Channel 0 * * * * * * * * * * * * * Register Used Timer clock select register (TCL3) Serial operation mode register 0 (CSIM0) Serial bus interface control register (SBIC) Interrupt timing specification register (SINT) Timer clock select register (TCL3) Serial operation mode register 1 (CSIM1) Automatic data transmission/reception control register (ADTC) Automatic data transmission/reception interval specification register (ADTI) Serial operation mode register 2 (CSIM2) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Serial interface pin select register (SIPS)Note Channel 1 Channel 2 Note This register is provided only on the PD780058, 780058Y, 780308, and 780308Y subseries. Remark This chapter describes the register formats and application examples of serial interface channels 0, 1, and 2. For details of the register formats of channels 3, 4, and 5, refer to the User's Manual of each subseries. 197 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-1. Format of Timer Clock Select Register 3 (PD78054, 78078, 780058, 78058F, 78075B subseries, PD78070A) Symbol 7 6 5 4 3 2 1 0 Address FF43H At reset 88H R/W R/W TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Selects serial clock of serial interface channel 0 MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Setting prohibited Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) TCL37 TCL36 TCL35 TCL34 Selects serial clock of serial interface channel 1 MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Setting prohibited Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Caution Before writing new data to TCL3, stop serial transfer once. Remarks 1. fXX 2. fX 4. ( : main system clock frequency (fX or fX/2) : main system clock oscillation frequency ) : at fX = 5.0 MHz 3. MCS : bit 0 of oscillation mode select register (OSMS) 198 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-2. Format of Timer Clock Select Register 3 (PD78054Y, 78078Y, 780058Y, 78058FY, 78075BY subseries, PD78070AY) Symbol 7 6 5 4 3 2 1 0 Address FF43H At reset 88H R/W R/W TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Selects serial clock of serial interface channel 0 Serial clock in 3-wire serial I/O or 2-wire Serial clock in I2C bus mode MCS = 1 MCS = 0 fX/26 fX/27 fX/28 fX/29 (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.77 kHz) (4.88 kHz) (2.44 kHz) (1.22 kHz) (0.61 kHz) fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 serial I/O mode MCS = 1 Setting prohibited fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) MCS = 0 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/210 fXX/211 fXX/212 Setting prohibited fX/26 fX/27 fX/28 fX/29 (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.77 kHz) (4.88 kHz) (2.44 kHz) (1.22 kHz) fX/210 fX/211 fX/212 fX/213 fX/210 fX/211 fX/212 Setting prohibited TCL37 TCL36 TCL35 TCL34 Selects serial clock of serial interface channel 1 MCS = 1 MCS = 0 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Setting prohibited Setting prohibited fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) Caution Before writing new data to TCL3, stop serial transfer once. Remarks 1. fXX 2. fX 4. ( : main system clock frequency (fX or fX/2) : main system clock oscillation frequency ) : at fX = 5.0 MHz 3. MCS : bit 0 of oscillation mode select register (OSMS) 199 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-3. Format of Timer Clock Select Register 3 (PD78064, 780308, 78064B subseries) Symbol TCL3 7 1 6 0 5 0 4 0 3 2 1 0 Address FF43H At reset 88H R/W R/W TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Selects serial clock of serial interface channel 0 MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Setting prohibited Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Cautions 1. Clear bits 4 through 6 to 0 and set bit 7 to 1. 2. Before writing new data to TCL3, stop serial transfer once. Remarks 1. fXX 2. fX 4. ( : main system clock frequency (fX or fX/2) : main system clock oscillation frequency ) : at fX = 5.0 MHz 3. MCS : bit 0 of oscillation mode select register (OSMS) 200 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-4. Format of Timer Clock Select Register 3 (PD78064Y, 780308Y subseries) Symbol TCL3 7 1 6 0 5 0 4 0 3 2 1 0 Address FF43H At reset 88H R/W R/W TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 Selects serial clock of serial interface channel 0 Serial clock in 3-wire serial I/O or Serial clock in I2C bus mode MCS = 1 MCS = 0 fXX/2 fXX/22 fXX/23 fXX/24 2-wire serial I/O mode MCS = 1 MCS = 0 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/210 fXX/211 fXX/212 Setting prohibited fX/26 (78.1 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.77 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.77 kHz) Setting prohibited fX/22 (1.25 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.88 kHz) fXX/25 fX/210 (4.88 kHz) fX/211 (2.44 kHz) fXX/26 fX/211 (2.44 kHz) fX/212 (1.22 kHz) fXX/27 fX/212 (1.22 kHz) fX/213 (0.61 kHz) fXX/28 Setting prohibited Cautions 1. Clear bits 4 through 6 to 0 and set bit 7 to 1. 2. Before writing new data to TCL3, stop serial transfer once. Remarks 1. fXX 2. fX 4. ( : main system clock frequency (fX or fX/2) : main system clock oscillation frequency ) : at fX = 5.0 MHz 3. MCS : bit 0 of oscillation mode select register (OSMS) 201 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-5. Format of Timer Clock Select Register 3 (PD78098, 78098B subseries) Symbol 7 6 5 4 3 2 1 0 Address FF43H At reset 88H R/W R/W TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 TCL33 TCL32 TCL31 TCL30 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2Note Selects serial clock of serial interface channel 0 fXX/22 (1.0 MHz) fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) Setting prohibited TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 Others 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fXX/2Note Selects serial clock of serial interface channel 1 fXX/22 (1.0 MHz) fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) Setting prohibited Note Can be set only when the main system clock frequency is 5.0 MHz or less. Caution Before writing new data to TCL3, stop serial transfer once. Remarks 1. fXX : main system clock frequency 2. ( ) : at fXX = 4.0 MHz 202 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-6. Format of Timer Clock Select Register 3 (PD780018, 780018Y subseries) Symbol 7 6 5 4 3 1 2 0 1 0 0 0 Address FF43H At reset 88H R/W R/W TCL3 TCL37 TCL36 TCL35 TCL34 TCL37 TCL36 TCL35 TCL34 0 1 1 1 1 1 1 Others 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 Selects serial clock of serial interface channel 1 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Setting prohibited Caution Before writing new data to TCL3, stop serial transfer once. Remarks 1. fXX : main system clock frequency (fX) 2. fX 3. ( : main system clock oscillation frequency ) : at fX = 5.0 MHz 203 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-7. Format of Serial Operating Mode Register 0 (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A)(1/2) Symbol CSIM0 7 6 5 4 3 2 1 0 Address FF60H At reset 00H R/W R/WNote 1 CSIE CSIM CSIM CSIM CSIM CSIM COI WUP 04 03 02 01 00 0 R/W CSIM CSIM 01 00 Selects clock of serial interface channel 0 0 1 1 x 0 1 Clock externally input to SCK0 pin Output of 8-bit timer register 2 (TM2) Clock specified by bits 0 through 3 of timer clock select register 3 (TCL3) R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operation mode First bit Function of Function of Function of 04 03 02 SI0/SB0/P25 pin SO0/SB1/P26 pin SCK0/P27 pin 0 x 0 1 Note 2 Note 2 0 0 0 1 3-wire serial I/O mode MSB LSB MSB SI0Note 2 (input) P25 (CMOS I/O) SO0 (CMOS output) SB1 SCK0 (CMOS I/O) SCK0 1 x 0 0 0 1 1 0 0 Note 3 Note 3 SBI mode x x (N-ch open drain (CMOS I/O) I/O) 1 0 0 Note 3 Note 3 x x 0 1 SB0 P26 (N-ch open drain (CMOS I/O) I/O) 0 1 2-wire serial I/O mode MSB P25 (CMOS I/O) SB1 SCK0 1 1 0 Note 3 Note 3 x x 0 0 (N-ch open drain (N-ch open drain I/O) I/O) P26 1 0 0 Note 3 Note 3 x x 0 1 SB0 (N-ch open drain (CMOS I/O) I/O) R/W WUP 0 1 Controls wake-up functionNote 4 Generates interrupt request signal in all modes each time serial transfer is executed Generates interrupt request signal when address received after bus has been released (when CMDD = RELD = 1) coincides with data of slave address register in SBI mode Notes 1. Bit 6 (COI) is a read-only bit. 2. When only the transmission function is used, this pin can be used as P25 (CMOS I/O). 3. These pins can be used as port pins. 4. When using the wake-up function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/SBI) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation. Remark x : don't care PMxx: Port mode register Pxx : Output latch of port 204 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-7. Format of Serial Operating Mode Register 0 (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A)(2/2) R COI Slave address comparison result flagNote Data of slave address register does not coincide with data of serial I/O shift register Data of slave address register coincides with data of serial I/O shift register 0 1 R/W CSIE0 0 1 Stops operation Enables operation Controls operation of serial interface channel 0 Note COI is 0 when CSIE0 = 0. Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/SBI) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation. 205 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-8. Format of Serial Operating Mode Register 0 (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, PD78070AY) (1/2) Symbol CSIM0 7 6 5 4 3 2 1 0 Address FF60H At reset 00H R/W R/WNote 1 CSIE CSIM CSIM CSIM CSIM CSIM COI WUP 04 03 02 01 00 0 R/W CSIM CSIM 01 00 Selects clock of serial interface channel 0 0 1 1 x 0 1 Clock externally input to SCK0/SCL pin Output of 8-bit timer register 2 (TM2)Note 2 Clock specified by bits 0 through 3 of timer clock select register 3 (TCL3) Function of Function of R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operation mode First bit Function of 04 03 02 SI0/SB0/SDA0/P25 pin SO0/SB1/SDA1/P26 pin SCK0/SCL/P27 pin Note 3 Note 3 0 x 0 1 1 x 0 0 0 1 3-wire serial I/O mode MSB LSB SI0Note 3 (input) P25 (CMOS I/O) SO0 (CMOS output) SCK0 (CMOS I/O) 1 1 0 Note 4 Note 4 0 0 0 1 x 1 0 x 0 Note 4 Note 4 2-wire serial MSB I/O mode or I2C bus mode SB1 SCK0/SCL (N-ch open drain (N-ch open drain I/O) I/O) 0 1 x x SB0/SDA0 P26 (N-ch open drain (CMOS I/O) I/O) R/W WUP 0 1 Controls wake-up functionNote 5 Generates interrupt request signal in all modes each time serial transfer is executed Generates interrupt request signal when address received after start condition has been detected (when CMDD = 1) coincides with data of slave address register in I2C mode Notes 1. Bit 6 (COI) is a read-only bit. 2. In the I2C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2 3. When only the transmission function is used, this pin can be used as P25 (CMOS I/O). 4. These pins can be used as port pins. 5. When using the wake-up function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. While WUP = 1, do not execute an instruction that writes data to the I/O shift register 0 (SIO0). Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/I2C bus) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation. Remark x : don't care PMxx: Port mode register Pxx : Output latch of port 206 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-8. Format of Serial Operating Mode Register 0 (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, PD78070AY) (2/2) R COI Slave address comparison result flagNote Data of slave address register does not coincide with data of serial I/O shift register Data of slave address register coincides with data of serial I/O shift register 0 1 R/W CSIE0 0 1 Stops operation Enables operation Controls operation of serial interface channel 0 Note COI is 0 when CSIE0 = 0. Caution Do not change the operation mode (3-wire serial I/O/2-wire serial I/O/I2C bus) while the operation of the serial interface channel 0 is enabled. To change the operation mode, stop the serial operation. 207 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-9. Format of Serial Bus Interface Control Register (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A) (1/2) Symbol SBIC 7 6 5 4 3 2 1 0 Address FF61H At reset 00H R/W R/W Note BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT R/W RELT Used to output bus release signal. When RELT = 1, SO latch is set to 1. After SO latch has been set, this bit is automatically cleared to 0. It is also cleared to 0 when CSIE = 0. R/W CMDT Used to output command signal. When CMDT = 1, SO latch is cleared to 0. After SO latch has been cleared, this bit is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0. R RELD Clear condition (RELD = 0) * On execution of transfer start instruction Bus release detection Set condition (RELD = 1) * When bus release signal (REL) is detected * If values of SIO0 and SVA do not coincide when address is received * When CSIE0 = 0 * At RESET input R CMDD Clear condition (CMDD = 0) * On execution of transfer start instruction Command detection Set condition (CMDD = 1) * When command signal (CMD) is detected * When bus release signal (REL) is detected * When CSIE0 = 0 * At RESET input R/W ACKT Outputs acknowledge signal in synchronization with falling edge of SCK0 clock immediately after instruction that sets this bit to 1 has been executed. After acknowledge signal has been output, this bit is automatically cleared to 0. ACKE is cleared to 0. This bit is also cleared to 0 when transfer of serial interface is started and when CSIE0 = 0. Note Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits. Remarks 1. Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are cleared to 0 when they are read after data has been set. 2. CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0) 208 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-9. Format of Serial Bus Interface Control Register (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A) (2/2) R/W ACKE 0 1 Controls acknowledge signal output Disables automatic output of acknowledge signal (output by ACKT is enabled) Before completion of transfer After completion of transfer Acknowledge signal is output in synchronization with falling edge of 9th clock of SCK0 (automatically output when ACKE = 1) Acknowledge signal is output in synchronization with falling edge of SCK0 clock immediately after instruction that sets this bit to 1 has been executed (automatically output when ACKE = 1). However, this bit is not automatically cleared to 0 after acknowledge signal has been output. Acknowledge detection Set condition (ACKD = 1) * When acknowledge signal (ACK) is detected at rising edge of SCK0 clock after completion of transfer R ACKD Clear condition (ACKD = 0) * Falling edge of SCK0 clock immediately after busy mode has been released after execution of transfer start instruction * When CSIE0 = 0 * At RESET input R/W BSYENote 0 Controls output of synchronization busy signal Disables output of busy signal in synchronization with falling edge of SCK0 clock immediately after instruction that clears this bit to 0 has been executed Outputs busy signal at falling edge of SCK0 clock following acknowledge signal 1 Note The busy mode can be released by starting serial interface transfer and receiving of an address signal. However, the BSYE flag is not cleared to 0. Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0) 209 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-10. Format of Serial Bus Interface Control Register (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, PD78070AY) (1/2) Symbol SBIC R/W 7 6 5 4 3 2 1 0 Address FF61H At reset 00H R/W R/W Note BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT Used to output stop condition. When RELT = 1, SO latch is set to 1. After SO latch has been set, this bit is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0. R/W CMDT Used to output start condition. When CMDT = 1, SO latch is cleared to 0. After SO latch has been cleared, this bit is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0. R RELD Clear condition (RELD = 0) * On execution of transfer start instruction Stop condition detection Set condition (RELD = 1) * Stop condition is detected * If values of SIO0 and SVA do not coincide when address is received * When CSIE0 = 0 * At RESET input R CMDD Clear condition (CMDD = 0) Start condition detection Set condition (CMDD = 1) * When start condition is detected * On execution of transfer start instruction * When stop condition is detected * When CSIE0 = 0 * At RESET input R/W ACKT Makes SDA0 (SDA1) low immediately after instruction that sets this bit to 1 (ACKT = 1) until next SCL falls. Used to generate ACK signal by software when 8-clock wait is selected. Cleared to 0 when transfer by serial interface is started and CSIE0 = 0 Note Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits. Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0) 210 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-10. Format of Serial Bus Interface Control Register (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, PD78070AY) (2/2) R/W ACKE 0 Controls automatic output of acknowledge signalNote 1 Disables automatic output of acknowledge signal (output by ACKT is enabled). Used for transmission or reception with 8-clock wait selectedNote 2. Enables automatic output of acknowledge signal. Acknowledge signal is output in synchronization with falling edge of 9th clock of SCL (automatically output when ACKE = 1). After output, this bit is not automatically cleared to 0. Used for reception when 9-clock wait is selected. 1 R ACKD Clear condition (ACKD = 0) * On execution of transfer start instruction * When CSIE0 = 0 * At RESET input Acknowledge detection Set condition (ACKD = 1) * When acknowledge signal is detected at rising edge of SCL clock after completion of transfer R/W BSYENote 3 0 1 Controls transmission N-ch open drain output in I2C bus modeNote 4 Enables output (transmission) Disables output (reception) Notes 1. Set this bit before starting transfer. 2. Output the acknowledge signal on reception by using ACKT when 8-clock wait is selected. 3. The wait status can be released by starting transfer of serial interface or receiving an address signal. However, BSYE is not cleared to 0. 4. Be sure to set BSYE to 1 when using the wake-up function. Remark CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0) 211 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-11. Format of Interrupt Timing Specification Register (PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B, 78098B subseries, PD78070A) Symbol SINT 7 0 6 CLD 5 SIC 4 SVAM 3 0 2 0 1 0 0 0 Address FF63H At reset 00H R/W R/W Note 1 R/W SVAM 0 1 Bits of SVA used as slave address Bits 0 through 7 Bits 1 through 7 Selects INTCSI0 interrupt sourceNote 2 Sets CSIIF0 at end of transfer of serial interface channel 0 Sets CSIIF0 at end of transfer of serial interface channel 0 or on detection of bus release Level of SCK0 pinNote 3 Low level High level R/W SIC 0 1 R CLD 0 1 Notes 1. Bit 6 (CLD) is a read-only bit. 2. Clear SIC to 0 when using the wake-up function in the SBI mode. 3. CLD is 0 when CSIE0 = 0. Caution Be sure to clear bits 0 through 3 to 0. Remark SVA : slave address register CSIIF0 : interrupt request flag corresponding to INTCSI0 CSIE0 : bit 7 of the serial operating mode register 0 (CSIM0) 212 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-12. Format of Interrupt Timing Specification Register (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, PD78070AY) (1/2) Symbol SINT 7 0 6 CLD 5 SIC 4 SVAM 3 CLC 2 1 0 Address FF63H At reset 00H R/W R/W Note 1 WREL WAT1 WAT0 R/W WAT1 WAT0 0 0 Controls wait and interrupt processing request Generates interrupt request at rising edge of 8th clock of SCK0 (clock output goes into high-impedance state) Setting prohibited Used in I2C bus mode (8-clock wait). Generates interrupt processing request at rising edge of 8th clock of SCL (master makes SCL output low and waits after outputting 8 clocks. Slave makes SCL pin low and requests for wait after inputting 8 clocks). Used in I2C bus mode (9-clock wait). Generates interrupt processing request at rising edge of 9th clock of SCL (master makes SCL output low and waits after outputting 9 clocks. Slave makes SCL pin low and requests for wait after inputting 9 clocks). 0 1 1 0 1 1 R/W WREL 0 1 Wait release status Controls wait release Releases wait status. After wait status has been released, this bit is automatically cleared to 0 (used to release wait status set by WAT1 and WAT0) R/W CLC 0 Controls clock levelNote 2 Used in I2C bus mode. Makes output level of SCL pin low when serial transfer is not executed Used in I2C bus mode. Makes output level of SCL pin high impedance when serial transfer is not executed (clock line goes high). Used by master to generate start/stop condition. 1 Notes 1. Bit 6 (CLD) is a read-only bit. 2. Clear CLC to 0 when the I2C bus mode is not used. 213 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-12. Format of Interrupt Timing Specification Register (PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, PD78070AY) (2/2) R/W SVAM 0 1 Bits 0 through 7 Bits 1 through 7 Bits of SVA used as slave address R/W SIC 0 1 Selects INTCSI0 interrupt sourceNote 1 Sets CSIIF0 to 1 at end of transfer of serial interface channel 0 Sets CSIIF0 to 1 at end of transfer of serial interface channel 0 or on detection of stop condition R/W CLD 0 1 Low level High level Level of SCK0/SCL/P27 pinNote 2 Notes 1. Sets SIC to 1 when using the wake-up function in the I2C mode. 2. CLD is 0 when CSIE0 = 0. Remark SVA : slave address register CSIIF0 : interrupt request flag corresponding to INTCSI0 CSIE0 : bit 7 of the serial operating mode register 0 (CSIM0) 214 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-13. Format of Serial Operating Mode Register 1 (PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) Symbol 7 6 5 4 0 3 0 2 0 1 0 Address FF68H At reset 00H R/W R/W CSIE CSIM1 DIR ATE 1 CSIM CSIM 11 10 CSIM CSIM 11 10 Selects clock of serial interface channel 1 Clock externally input to SCK1 pinNote 1 Output of 8-bit timer register 2 (TM2) Clock specified by bits 4 through 7 of timer clock select register 3 (TCL3) Selects operation mode of serial interface channel 1 0 1 1 ATE x 0 1 0 1 3-wire serial I/O mode 3-wire serial I/O mode with automatic transfer/reception function DIR First bit MSB LSB Function of SI1 pin SI1/P20 (input) Controls operation Function of of counter of SI1/P20 pin serial clock Clear P20 (CMOS I/O) Count operation SI1Note 3 (input) Function of SO1 pin SO1 (CMOS output) 0 1 CSIE CSIM PM20 P20 PM21 P21 PM22 P22 1 11 Operation of shift register 1 Stops operation Enables operation Function of SO1/P21 pin P21 (CMOS I/O) SO1 Function of SCK1/P22 P22 (CMOS I/O) SCK1 0 x Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 x 1 0 x x 0 x 0 x 1 x x Note 3 Note 3 1 1 x 0 1 (CMOS output) (input) SCK1 (CMOS output) Notes 1. Clear bit 2 (STRB) and bit 1 (BUSY1) of the automatic data transfer/reception control register (ADTC) to 0, 0 when the external clock input is selected by clearing CSIM11 to 0. 2. These pins can be used as port pins. 3. When only transmit is executed, this pin can be used as P20 (CMOS I/O). (Set bit 7 (RE) of the automatic data transfer/reception control register (ADTC) to 0.) Remark x : don't care PMxx: Port mode register Pxx : Output latch of port 215 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-14. Format of Automatic Data Transfer/Reception Control Register (PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) Symbol ADTC 7 RE 6 5 4 ERR 3 TRF 2 1 0 Address FF69H At reset 00H R/W R/W Note 1 ARLD ERCE STRB BUSY1 BUSY0 R/W BUSY1 BUSY0 Controls busy input 0 1 1 x 0 1 Does not use busy input Enables busy input (active high) Enables busy input (low active) R/W STRB 0 1 Controls strobe output Disables strobe output Enables strobe output Note 2 R TRF 0 Status of automatic transfer/reception function Detects end of automatic transfer/reception (0 when automatic transfer/reception is stopped or when ARLD = 0) Automatic transfer/reception in progress (1 when SIO1 is written) 1 R ERR 0 1 Detects error of automatic transfer/reception function No error on automatic reception (0 when 1 is written to SIO1) Error on automatic transfer/reception R/W ERCE 0 1 Controls error check of automatic transfer/reception function Disables error check on automatic transfer/reception Enables error check on automatic transfer/reception (only when BUSY1 = 1) R/W ARLD 0 1 Selects operation mode of automatic transfer/ reception function Single mode Repetitive mode R/W RE 0 1 Controls reception of automatic transfer/reception function Disables reception Enables reception Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. Identify the end of automatic transfer/reception by using TRF instead of CSIIF1. (interrupt request flag) Caution When external clock input is selected by clearing bit 1 (CSIM11) of the serial operating mode register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0. Remark x: don't care 216 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-15. Format of Automatic Data Transfer/Reception Control Register (PD780058, 780058Y subseries) Symbol ADTC 7 RE 6 5 4 ERR 3 TRF 2 1 0 Address FF69H At reset 00H R/W R/W Note 1 ARLD ERCE STRB BUSY1 BUSY0 R/W BUSY1 BUSY0 Controls busy input 0 1 1 x 0 1 Does not use busy input Enables busy input (active high) Enables busy input (low active) R/W STRB 0 1 Controls strobe output Disables strobe output Enables strobe output Note 2 R TRF 0 Status of automatic transfer/reception function Detects end of automatic transfer/reception (0 when automatic transfer/reception is stopped or when ARLD = 0) Automatic transfer/reception in progress (1 when SIO1 is written) 1 R ERR 0 1 Detects error of automatic transfer/reception function No error on automatic reception (0 when 1 is written to SIO1) Error on automatic transfer/reception R/W ERCE 0 1 Controls error check of automatic transfer/reception function Disables error check on automatic transfer/reception Enables error check on automatic transfer/reception (only when BUSY1 = 1) R/W ARLD 0 1 Selects operation mode of automatic transfer/ reception function Single mode Repetitive mode R/W RE 0 1 Controls reception of automatic transfer/reception function Disables reception Enables reception Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. Identify the end of automatic transfer/reception by using TRF instead of CSIIF1. (interrupt request flag) Cautions 1. When external clock input is selected by clearing bit 1 (CSIM11) of the serial operating mode register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0. 2. When using the P23/STB/TxD1 and P24/BUSY/RxD1 pins in the asynchronous serial interface (UART) mode of serial interface channel 2, the busy control option and busy & strobe control option are invalid. Remark x: don't care 217 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY subseries, PD78070A, 78070AY) (1/4) Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH At reset 00H R/W R/W ADTI ADTI7 ADTI7 0 1 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Controls interval time of data transfer Does not control interval time by ADTINote 1 Controls interval time by ADTI (ADTI0 through ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Specifies interval time of data transfer (fXX = 5.0 MHz) Minimum valueNote 2 Maximum valueNote 2 20.0 s + 1.5/fSCK 32.8 s + 1.5/fSCK 45.6 s + 1.5/fSCK 58.4 s + 1.5/fSCK 71.2 s + 1.5/fSCK 84.0 s + 1.5/fSCK 96.8 s + 1.5/fSCK 109.6 s + 1.5/fSCK 122.4 s + 1.5/fSCK 135.2 s + 1.5/fSCK 148.0 s + 1.5/fSCK 160.8 s + 1.5/fSCK 173.6 s + 1.5/fSCK 186.4 s + 1.5/fSCK 199.2 s + 1.5/fSCK 212.0 s + 1.5/fSCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 18.4 s + 0.5/fSCK 31.2 s + 0.5/fSCK 44.0 s + 0.5/fSCK 56.8 s + 0.5/fSCK 69.6 s + 0.5/fSCK 82.4 s + 0.5/fSCK 95.2 s + 0.5/fSCK 108.0 s + 0.5/fSCK 120.8 s + 0.5/fSCK 133.6 s + 0.5/fSCK 146.4 s + 0.5/fSCK 159.2 s + 0.5/fSCK 172.0 s + 0.5/fSCK 184.8 s + 0.5/fSCK 197.6 s + 0.5/fSCK 210.4 s + 0.5/fSCK Notes 1. The interval time is dependent on only the CPU processing. 2. The interval time of data transfer includes an error. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/fSCK, the minimum interval time is 2/fSCK. Minimum value = (n+1) x 26 fXX 26 fXX + 28 fXX 36 fXX + 0.5 fSCK 1.5 fSCK Maximum value = (n+1) x + + 218 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Cautions 1. Do not write ADTI during automatic transmission/reception operation. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid. Remarks 1. fXX : main system clock frequency (fX or fX/2) 2. fX : main system clock oscillation frequency 3. fSCK: serial clock frequency 219 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY subseries, PD78070A, 78070AY) (2/4) Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH At reset 00H R/W R/W ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Specifies interval time of data transfer (fXX = 5.0 MHz) Minimum valueNote Maximum valueNote 224.8 s + 1.5/fSCK 237.6 s + 1.5/fSCK 250.4 s + 1.5/fSCK 263.2 s + 1.5/fSCK 276.0 s + 1.5/fSCK 288.8 s + 1.5/fSCK 301.6 s + 1.5/fSCK 314.4 s + 1.5/fSCK 327.2 s + 1.5/fSCK 340.0 s + 1.5/fSCK 352.8 s + 1.5/fSCK 365.6 s + 1.5/fSCK 378.4 s + 1.5/fSCK 391.2 s + 1.5/fSCK 404.0 s + 1.5/fSCK 416.8 s + 1.5/fSCK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 223.2 s + 0.5/fSCK 236.0 s + 0.5/fSCK 248.8 s + 0.5/fSCK 261.6 s + 0.5/fSCK 274.4 s + 0.5/fSCK 287.2 s + 0.5/fSCK 300.0 s + 0.5/fSCK 312.8 s + 0.5/fSCK 325.6 s + 0.5/fSCK 338.4 s + 0.5/fSCK 351.2 s + 0.5/fSCK 364.0 s + 0.5/fSCK 376.8 s + 0.5/fSCK 389.6 s + 0.5/fSCK 402.4 s + 0.5/fSCK 415.2 s + 0.5/fSCK Note The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/fSCK, the minimum interval time is 2/fSCK. Minimum value = (n+1) x 26 fXX 26 fXX + 28 fXX 36 fXX + 0.5 fSCK 1.5 fSCK Maximum value = (n+1) x + + Cautions 1. Do not write ADTI during automatic transfer/reception operation. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid. Remarks 1. fXX : main system clock frequency (fX or fX/2) 2. fX : main system clock oscillation frequency 3. fSCK: serial clock frequency 220 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY subseries, PD78070A, 78070AY) (3/4) Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH At reset 00H R/W R/W ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 0 1 Controls interval time of data transfer Does not control interval time by ADTINote 1 Controls interval time by ADTI (ADTI0 through ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Specifies interval time of data transfer (fXX = 2.5 MHz) Minimum valueNote 2 Maximum valueNote 2 40.0 s + 1.5/fSCK 65.6 s + 1.5/fSCK 91.2 s + 1.5/fSCK 116.8 s + 1.5/fSCK 142.4 s + 1.5/fSCK 168.0 s + 1.5/fSCK 193.6 s + 1.5/fSCK 219.2 s + 1.5/fSCK 244.8 s + 1.5/fSCK 270.4 s + 1.5/fSCK 296.0 s + 1.5/fSCK 321.6 s + 1.5/fSCK 347.2 s + 1.5/fSCK 372.8 s + 1.5/fSCK 398.4 s + 1.5/fSCK 424.0 s + 1.5/fSCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 36.8 s + 0.5/fSCK 62.4 s + 0.5/fSCK 88.0 s + 0.5/fSCK 113.6 s + 0.5/fSCK 139.2 s + 0.5/fSCK 164.8 s + 0.5/fSCK 190.4 s + 0.5/fSCK 216.0 s + 0.5/fSCK 241.6 s + 0.5/fSCK 267.2 s + 0.5/fSCK 292.8 s + 0.5/fSCK 318.4 s + 0.5/fSCK 344.0 s + 0.5/fSCK 369.6 s + 0.5/fSCK 395.2 s + 0.5/fSCK 420.8 s + 0.5/fSCK Notes 1. The interval time is dependent on only the CPU processing. 2. The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/fSCK, the minimum interval time is 2/fSCK. Minimum value = (n+1) x 26 fXX 26 fXX + 28 fXX 36 fXX + 0.5 fSCK 1.5 fSCK Maximum value = (n+1) x + + 221 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Cautions 1. Do not write ADTI during automatic transfer/reception operation. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid. Remarks 1. fXX : main system clock frequency (fX or fX/2) 2. fX : main system clock oscillation frequency 3. fSCK: serial clock frequency 222 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-16. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78054, 78054Y, 78078, 78078Y, 780018, 780018Y, 780058, 780058Y, 78058F, 78058FY, 78075B, 78075BY subseries, PD78070A, 78070AY) (4/4) Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH At reset 00H R/W R/W ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Specifies interval time of data transfer (fXX = 2.5 MHz) Minimum valueNote Maximum valueNote 449.6 s + 1.5/fSCK 475.2 s + 1.5/fSCK 500.8 s + 1.5/fSCK 526.4 s + 1.5/fSCK 552.0 s + 1.5/fSCK 577.6 s + 1.5/fSCK 603.2 s + 1.5/fSCK 628.8 s + 1.5/fSCK 654.4 s + 1.5/fSCK 680.0 s + 1.5/fSCK 705.6 s + 1.5/fSCK 731.2 s + 1.5/fSCK 756.8 s + 1.5/fSCK 782.4 s + 1.5/fSCK 808.0 s + 1.5/fSCK 833.6 s + 1.5/fSCK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 446.4 s + 0.5/fSCK 472.0 s + 0.5/fSCK 497.6 s + 0.5/fSCK 523.2 s + 0.5/fSCK 548.8 s + 0.5/fSCK 574.4 s + 0.5/fSCK 600.0 s + 0.5/fSCK 625.6 s + 0.5/fSCK 651.2 s + 0.5/fSCK 676.8 s + 0.5/fSCK 702.4 s + 0.5/fSCK 728.0 s + 0.5/fSCK 753.6 s + 0.5/fSCK 779.2 s + 0.5/fSCK 804.8 s + 0.5/fSCK 830.4 s + 0.5/fSCK Note The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/fSCK, the minimum interval time is 2/fSCK. Minimum value = (n+1) x 26 fXX 26 fXX + 28 fXX 36 + fXX + + 0.5 fSCK 1.5 fSCK Maximum value = (n+1) x Cautions 1. Do not write ADTI during automatic transfer/reception operation. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid. Remarks 1. fXX : main system clock frequency (fX or fX/2) 2. fX : main system clock oscillation frequency 3. fSCK: serial clock frequency 223 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-17. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78098, 78098B subseries) (1/2) Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH At reset 00H R/W R/W ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI7 0 1 Controls interval time of data transfer Does not control interval time by ADTINote 1 Controls interval time by ADTI (ADTI0 through ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Specifies interval time of data transfer (fXX = 4.0 MHz) Minimum valueNote 2 Maximum valueNote 2 25.0 s + 1.5/fSCK 41.0 s + 1.5/fSCK 57.0 s + 1.5/fSCK 73.0 s + 1.5/fSCK 89.0 s + 1.5/fSCK 105.0 s + 1.5/fSCK 121.6 s + 1.5/fSCK 137.0 s + 1.5/fSCK 153.0 s + 1.5/fSCK 169.0 s + 1.5/fSCK 185.0 s + 1.5/fSCK 201.0 s + 1.5/fSCK 217.0 s + 1.5/fSCK 233.0 s + 1.5/fSCK 249.0 s + 1.5/fSCK 265.0 s + 1.5/fSCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 23.0 s + 0.5/fSCK 39.0 s + 0.5/fSCK 55.0 s + 0.5/fSCK 71.0 s + 0.5/fSCK 87.0 s + 0.5/fSCK 103.0 s + 0.5/fSCK 119.0 s + 0.5/fSCK 135.0 s + 0.5/fSCK 151.0 s + 0.5/fSCK 167.0 s + 0.5/fSCK 183.0 s + 0.5/fSCK 199.0 s + 0.5/fSCK 215.0 s + 0.5/fSCK 231.0 s + 0.5/fSCK 247.0 s + 0.5/fSCK 263.0 s + 0.5/fSCK Notes 1. The interval time is dependent on only the CPU processing. 2. The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/fSCK, the minimum interval time is 2/fSCK. Minimum value = (n+1) x 26 fXX 26 fXX + 28 fXX 36 fXX + 0.5 fSCK 1.5 fSCK Maximum value = (n+1) x + + 224 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Cautions 1. Do not write ADTI during automatic transfer/reception operation. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid. Remarks 1. fXX : main system clock frequency 2. fSCK: serial clock frequency 225 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-17. Format of Automatic Data Transfer/Reception Interval Specification Register (PD78098, 78098B subseries) (2/2) Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH At reset 00H R/W R/W ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Specifies interval time of data transfer (fXX = 4.0 MHz) Minimum valueNote Maximum valueNote 281.0 s + 1.5/fSCK 297.0 s + 1.5/fSCK 313.0 s + 1.5/fSCK 329.0 s + 1.5/fSCK 345.0 s + 1.5/fSCK 361.0 s + 1.5/fSCK 377.0 s + 1.5/fSCK 393.0 s + 1.5/fSCK 409.0 s + 1.5/fSCK 425.0 s + 1.5/fSCK 441.0 s + 1.5/fSCK 457.0 s + 1.5/fSCK 473.0 s + 1.5/fSCK 489.0 s + 1.5/fSCK 505.0 s + 1.5/fSCK 521.0 s + 1.5/fSCK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 279.0 s + 0.5/fSCK 295.0 s + 0.5/fSCK 311.0 s + 0.5/fSCK 327.0 s + 0.5/fSCK 343.0 s + 0.5/fSCK 359.0 s + 0.5/fSCK 375.0 s + 0.5/fSCK 391.0 s + 0.5/fSCK 407.0 s + 0.5/fSCK 423.0 s + 0.5/fSCK 439.0 s + 0.5/fSCK 455.0 s + 0.5/fSCK 471.0 s + 0.5/fSCK 487.0 s + 0.5/fSCK 503.0 s + 0.5/fSCK 519.0 s + 0.5/fSCK Note The interval time of data transfer includes an error margin. The minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to ADTI0 through ADTI4). However, if the minimum value calculated by the expression below is less than 2/fSCK, the minimum interval time is 2/fSCK. Minimum value = (n+1) x 26 fXX 26 fXX + 28 fXX 36 fXX + 0.5 fSCK 1.5 fSCK Maximum value = (n+1) x + + Cautions 1. Do not write ADTI during automatic transfer/reception operation. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling interval time of data transfer by automatic transfer/reception using ADTI, the busy control option is invalid. Remarks 1. fXX : main system clock frequency 2. fSCK: serial clock frequency 226 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-18. Format of Serial Operating Mode Register 2 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) Symbol 7 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H At reset 00H R/W R/W CSIM2 CSIE2 CSIM22 CSCK CSCK 0 1 Selects clock in 3-wire serial I/O mode Clock externally input to SCK2 pin Output of dedicated baud rate generator CSIM22 Specifies first bit MSB LSB 0 1 CSIE2 0 1 Controls operation in 3-wire serial I/O mode Stops operation Enables operation Cautions 1. Be sure to clear bits 0 and 3 through 6 to 0. 2. Set CSIM2 to 00H in the UART mode. 227 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-19. Format of Asynchronous Serial Interface Mode Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) Symbol ASIM 7 TXE 6 RXE 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 SCK Address FF70H At reset 00H R/W R/W SCK 0 1 Selects clock of asynchronous serial interface mode Clock externally input to ASCK pin Output of dedicated baud rate generatorNote ISRM 0 1 Controls receive end interrupt on occurrence of error Generates receive end interrupt request when error occurs Does not generate receive end interrupt request when error occurs SL 0 1 Specifies stop bit length of transmit data 1 bit 2 bits CL 0 1 Specifies character length 7 bits 8 bits PS1 0 0 PS0 0 1 Specifies parity bit No parity Always append 0 parity during transmission. Does not check parity during reception (does not generate parity error) Odd parity Even parity 1 1 0 1 RXE 0 1 Controls reception operation Stops reception operation Enables reception operation TXE 0 1 Controls transmission operation Stops transmission operation Enables transmission operation Note When the baud rate generator output is selected by setting SCK to 1, the ASCK pin can be used as an I/O port pin. Cautions 1. Set ASIM to 00H when the 3-wire serial I/O mode is selected. 2. Before changing the operation mode, stop the serial transfer/reception operation. 228 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Table 8-4. Setting of Operation Modes of Serial Interface Channel 2 (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) (1) Operation stop mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72 First bit Shift clock Function of Function of Function of P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK pin 0 Others 0 x 0 x x xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 - - P70 pin P71 pin P72 TXE RXE SCK CSIE2CSIM22 CSCK Setting prohibited (2) 3-wire serial I/O mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72 First bit Shift clock Function of Function of Function of P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK pin 0 0 0 1 0 0 1Note 2 xNote 2 0 1 1 x 1 x 1 MSB External SI2Note 2 clock 1 0 Internal clock 1 1 0 1 LSB External SI2Note 2 clock 1 0 Internal clock Others Setting prohibited SO2 (CMOS output) SCK2 output SCK2 input pin SO2 (CMOS output) SCK2 output pin SCK2 input TXE RXE SCK CSIE2CSIM22 CSCK (3) Asynchronous serial interface mode ASIM CSIM2 PM70 P70 PM71 P71 PM72 P72 First bit Shift clock Function of Function of Function of P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK pin 1 0 0 0 0 0 xNote 1 xNote 1 0 1 1 x LSB External P70 clock 1 x xNote 1 xNote 1 xNote 1 xNote 1 0 0 0 1 1 x Internal clock 0 1 0 External RxD clock 1 x xNote 1 xNote 1 0 0 0 1 0 1 1 x Internal clock 1 1 0 External clock 1 xNote 1 xNote 1 Internal clock Others Setting prohibited TxD (CMOS output) P72 ASCK input P72 P71 ASCK input pin TxD (CMOS output) P72 pin ASCK input TXE RXE SCK CSIE2CSIM22 CSCK Notes 1. These pins can be used as port pins. 2. This pin can be used as P70 (CMOS I/O) when only transmission is executed. Remark x : don't care PMxx: port mode register Pxx : output latch of port 229 230 ASIM x 0 0 0 x Table 8-5. Setting of Operation Modes of Serial Interface Channel 2 (PD780058 and 780058Y Subseries) (1/2) (1) Operation stop mode CSIM2 x SIPS x x PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72 First bit Shift clock - Function of P70/SI2/RxD0 pin Function of P71/SO2/TxD0 pin Function of Function of Function of TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 P23/STB/TxD1 pin P24/BUSY/RxD1 pin P72/SCK2/ASCK pin - P70 P71 P23/STB P24/BUSY P72 Others Setting prohibited CHAPTER 8 (2) 3-wire serial I/O mode ASIM CSIM2 x SIPS x PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72 First bit Shift clock Function of P70/SI2/RxD0 pin Function of P71/SO2/TxD0 pin Function of Function of Function of APPLICATIONS OF SERIAL INTERFACE TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 0 0 0 1 0 0 1 1 1 0 1 1Note 2 xNote 2 0 1 xNote 1 xNote 1 xNote 1 xNote 1 1 0 1 0 x 1 x 1 P23/STB/TxD1 pin P24/BUSY/RxD1 pin P72/SCK2/ASCK pin MSB External SI2Note 2 clock Internal clock SO2 (CMOS output) SO2 (CMOS output) P23/STB P24/BUSY SCK2 input SCK2 output SCK2 input SCK2 output LSB External SI2Note 2 clock Internal clock Others Setting prohibited Notes 1. These pins can be used as port pins. 2. This pin can be used as P70 (CMOS I/O) when only transmission is executed. Remark x : don't care PMxx: port mode register Pxx : output latch of port Table 8-5. Setting of Operation Modes of Serial Interface Channel 2 (PD780058 and 780058Y Subseries) (2/2) (3) Asynchronous serial interface mode ASIM CSIM2 SIPS PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72 First bit Shift clock Function of P70/SI2/RxD0 pin Function of P71/SO2/TxD0 pin Function of Function of Function of TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 x 0 1 0 1 1 x 0 0 0 0 1 1 x xNote xNote xNote xNote 1 x 0 0 0 1 0 xNote xNote 0 1 0 1 xNote xNote 0 0 0 0 0 1 x 0 1 xNote xNote xNote xNote 0 0 0 0 0 1 x xNote xNote xNote xNote xNote xNote 0 0 0 0 0 xNote xNote 0 1 xNote xNote xNote xNote 1 x P23/STB/TxD1 pin P24/BUSY/RxD1 pin P72/SCK2/ASCK pin LSB External P70 clock Internal clock External RxD0 clock Internal clock External clock Internal clock External P70 clock Internal clock External P70 clock Internal (input) clock External P70 clock Internal (input) clock TxD0 (CMOS output) P71 P23/STB P24/BUSY ASCK input P72 CHAPTER 8 ASCK input P72 xNote xNote 1 x xNote xNote 1 x TxD0 (CMOS output) Output high TxD1 P24/BUSY ASCK input P72 ASCK input P72 APPLICATIONS OF SERIAL INTERFACE xNote xNote 1 x xNote xNote 1 x P71 P23/STB RxD1 ASCK input P72 xNote xNote 1 x Output high TxD1 RxD1 ASCK input P72 xNote xNote Others Setting prohibited Note These pins can be used as port pins. Remark x : don't care PMxx: port mode register Pxx : output latch of port 231 Table 8-6. Setting of Operation Modes of Serial Interface Channel 2 (PD780308 and 780308Y Subseries) (1/2) (1) Operation stop mode ASIM x 232 0 0 0 x CSIM2 x SIPS x x PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72 First bit Shift clock - Function of P70/SI2/RxD0 pin Function of P71/SO2/TxD0 pin Function of P113/TxD pin Function of P114/RxD pin Function of P72/SCK2/ASCK pin TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 - P70 P71 P113 P114 P72 Others Setting prohibited CHAPTER 8 (2) 3-wire serial I/O mode ASIM CSIM2 x SIPS x PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72 First bit Shift clock Function of P70/SI2/RxD0 pin Function of P71/SO2/TxD0 pin Function of P113/TxD pin Function of Function of APPLICATIONS OF SERIAL INTERFACE TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 0 0 0 1 0 0 1 1 1 0 1 1Note 2 xNote 2 0 1 xNote 1 xNote 1 xNote 1 xNote 1 1 0 1 0 x 1 x 1 P114/RxD pin P72/SCK2/ASCK pin MSB External SI2Note 2 clock Internal clock SO2 (CMOS output) SO2 (CMOS output) P113 P114 SCK2 input SCK2 output SCK2 input SCK2 output LSB External SI2Note 2 clock Internal clock Others Setting prohibited Notes 1. These pins can be used as port pins. 2. This pin can be used as P70 (CMOS I/O) when only transmission is executed. Remark x : don't care PMxx: port mode register Pxx : output latch of port Table 8-6. Setting of Operation Modes of Serial Interface Channel 2 (PD780308 and 780308Y Subseries) (2/2) (3) Asynchronous serial interface mode ASIM CSIM2 SIPS PM70 P70 PM71 P71 PM113 P113 PM114 P114 PM72 P72 First bit Shift clock Function of P70/SI2/RxD0 pin Function of P71/SO2/TxD0 pin Function of P113/TxD pin Function of Function of TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 x 0 1 0 1 1 x 0 0 0 0 1 1 x xNote xNote xNote xNote 1 x 0 0 0 1 0 xNote xNote 0 1 0 1 xNote xNote 0 0 0 0 0 1 x 0 1 xNote xNote xNote xNote 0 0 0 0 0 1 x xNote xNote xNote xNote xNote xNote 0 0 0 0 0 xNote xNote 0 1 xNote xNote xNote xNote 1 x P114/RxD pin P72/SCK2/ASCK pin LSB External P70 clock Internal clock External RxD clock Internal clock External clock Internal clock External P70 clock Internal clock External P70 clock Internal (input) clock External P70 clock Internal (input) clock TxD (CMOS output) P71 P113 P114 ASCK input P72 CHAPTER 8 ASCK input P72 xNote xNote 1 x xNote xNote 1 x TxD (CMOS output) Output high TxD P114 ASCK input P72 ASCK input P72 APPLICATIONS OF SERIAL INTERFACE xNote xNote 1 x xNote xNote 1 x P71 P113 RxD ASCK input P72 xNote xNote 1 x Output high TxD RxD ASCK input P72 xNote xNote Others Setting prohibited Note These pins can be used as port pins. Remark x : don't care PMxx: port mode register Pxx : output latch of port 233 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-20. Format of Asynchronous Serial Interface Status Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 78098, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) Symbol ASIS 7 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address FF71H At reset 00H R/W R OVE 0 1 Overrun error flag Overrun error does not occur Overrun error occursNote 1 (if next reception operation is completed before data is read from receive buffer register) FE 0 1 Framing error flag Framing error does not occur Framing error occursNote 2 (if stop bit is not detected) PE 0 1 Parity error flag Parity error does not occur Parity error occurs (if parity of transmit data does not coincide) Notes 1. If an overrun error occurs, be sure to read the receive buffer register (RXB). The overrun error persists each time data is received until RXB is read. 2. Even if the stop bit length is set to 2 bits by the bit 2 (SL) of the asynchronous serial interface mode register (ASIM), only 1 stop bit is detected during reception. 234 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-21. Format of Baud Rate Generator Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) (1/2) Symbol BRGC 7 TPS3 6 TPS2 5 TPS1 4 TPS0 3 2 1 0 Address FF73H At reset 00H R/W R/W MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selects input clock of baud rate generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 fSCKNote k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - Note Can be used only in the 3-wire serial I/O mode. Remarks 1. fSCK: source clock of 5-bit counter 2. k : value set by MDL0 through MDL3 (0 k 14) 235 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-21. Format of Baud Rate Generator Control Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) (2/2) TPS3 TPS2 TPS1 TPS0 Selects source clock of 5-bit counter MCS = 1 0 0 0 0 1 1 1 1 1 1 1 Others 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fX/210 (4.9 kHz) fX/211 MCS = 0 (2.4 kHz) 11 1 2 3 4 5 6 7 8 9 10 n fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) fX/2 (2.5 MHz) fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) fX/210 Setting prohibited Caution If data is written to BRGC during communication, the output of the baud rate generator is disturbed and communication cannot be executed normally. Therefore, do not write data to BRGC during communication. Remarks 1. fXX 2. fX 4. n 5. ( : main system clock frequency (fX or fX/2) : main system clock oscillation frequency : value set by TPS0 through TPS3 (1 n 11) ) : at fX = 5.0 MHz 3. MCS : bit 0 of oscillation mode select register (OSMS) 236 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-22. Format of Baud Rate Generator Control Register (PD78098, 78098B subseries) (1/2) Symbol BRGC 7 TPS3 6 TPS2 5 TPS1 4 TPS0 3 2 1 0 Address FF73H At reset 00H R/W R/W MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selects input clock of baud rate generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 fSCKNote k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - Note Can be used only in the 3-wire serial I/O mode. Remarks 1. fSCK : source clock of 5-bit counter 2. k : value set by MDL0 through MDL3 (0 k 14) 237 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-22. Format of Baud Rate Generator Control Register (PD78098, 78098B subseries) (2/2) TPS3 0 0 0 0 1 1 1 1 1 1 1 Others TPS2 TPS1 TPS0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Selects source clock of 5-bit counter fXX/210 (3.91 kHz) fXX (4.0 MHz) fXX/2 (2.0 MHz) fXX/22 (1.0 MHz) fXX/23 (500 kHz) fXX/24 (250 kHz) fXX/25 (125 kHz) fXX/26 (62.5 kHz) fXX/27 (31.3 kHz) fXX/28 (15.6 kHz) fXX/29 (7.81 kHz) Setting prohibited n 11 1 2 3 4 5 6 7 8 9 10 Caution If data is written to BRGC during communication, the output of the baud rate generator is disturbed and communication cannot be executed normally. Therefore, do not write data to BRGC during communication. Remarks 1. fXX : main system clock frequency 2. n : value set by TPS0 through TPS3 (1 n 11) 3. ( ) : at fXX = 4.0 MHz 238 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-23. Format of Serial Interface Pin Select Register (PD780058 and 780058Y Subseries) Symbol SIPS 7 0 6 0 5 4 3 0 2 0 1 0 0 0 Address FF75H At reset 00H R/W R/W SIPS21 SIPS20 SIPS21 SIPS20 Selects I/O pin of asynchronous serial interface Input pin : RxD0/SI2/P70 Output pin : TxD0/SO2/P71 Input pin : RxD1/BUSY/P24 Output pin : TxD0/SO2/P71 Input pin : RxD0/SI2/P70 Output pin : TxD1/STB/P23 Input pin : RxD1/BUSY/P24 Output pin : TxD1/STB/P23 0 0 0 1 1 0 1 1 Cautions 1. Change the mode of an I/O Pin after stopping the serial transfer/reception operation. 2. When using the busy control option or busy & strobe control option in the 3-wire serial I/O mode with automatic transfer/reception function of the serial interface channel 1, the RxD1/ BUSY/P24 and TxD1/STB/P23 pins cannot be used as data I/O pins. Figure 8-24. Format of Serial Interface Pin Select Register (PD780308 and 780308Y Subseries) Symbol SIPS 7 0 6 0 5 4 3 0 2 0 1 0 0 0 Address FF75H At reset 00H R/W R/W SIPS21 SIPS20 SIPS21 SIPS20 Selects I/O pin of asynchronous serial interface Input pin : RxD/SI2/P70 Output pin : TxD/SO2/P71 Input pin : RxD/P114 Output pin : TxD/SO2/P71 Input pin : RxD0/SI2/P70 Output pin : TxD/P113 Input pin : RxD/P114 Output pin : TxD/P113 0 0 0 1 1 0 1 1 Cautions 1. Change the mode of an I/O Pin after stopping the serial transfer/reception operation. 2. Port 11 has a falling edge detection function. Do not input a falling edge to the pin used as a multiplexed pin of this port. 239 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.1 Interface with EEPROMTM (PD6252) The PD6252Note is a 2048-bit EEPROM which can be electrically written or erased. To write or read data to or from the PD6252, the 3-wire serial interface is used. Note PD6252 is for maintenance use. Figure 8-25. Pin Configuration of PD6252 CE IC IC GND 1 2 3 4 8 7 6 5 VDD CS SCL SDA 240 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Table 8-7. Pin Function of PD6252 Pin Number Pin Name 1 CE I/O CMOS input Function Keep this pin high during data transfer. Caution Do not change the level of this pin from high to low during data transfer. To change the level of this pin from high to low, make sure that the CS pin (pin 7) is low. By making both the CE and CS pins low, you can set the standby status in which the power consumption is reduced. 2 3 4 5 IC - Fix the IC pins to the high or low level via resistor. GND SDA - Ground CMOS input/ Data input/output pin. N-ch open-drain Because this pin is an N-ch open-drain I/O pin, externally pull it up with a resistor. output SDA 6 7 SCL CS CMOS input CMOS input Inputs a clock for data transfer. Chip select pin. When this pin is high, the PD6252 is enabled to operate. When it is low, memory cells cannot be read or written. When the level of this pin is changed from high to low with the SCL pin high, the operation of the serial bus interface is started. To end the operation of the serial bus interface, change the level of this pin from high to low. Positive power: +5 V 10% 8 VDD - 241 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.1.1 Communication in 2-wire serial I/O mode The 3-wire mode of the PD6252Note is implemented by serial clock (SCL), data (SDA), and chip select (CS) lines. Excluding the handshaking line, therefore, only two lines, clock and data lines, are necessary for interfacing. To interface the PD6252 with a 78K/0 series microcontroller, the 2-wire serial I/O mode is used. In the example shown in this section, the PD78054 subseries is used. Note PD6252 is for maintenance use. Figure 8-26. Example of Connection of PD6252 PD78054 PD6252 VDD VDD SCK0 SCL CE SB1 SDA P32 CS Table 8-8 and Figure 8-27 shows the commands to write and read data to/from the PD6252 and communication format. Table 8-8. PD6252 Commands Command Name RANDOM WRITE Command 00000000B [00H] MSB C7-C0 Operation Transfers write data after setting an 8-bit word address (WA). Up to 3 bytes of write data can be set successively. Correspondence between word address and data WA Data of first byte WA+1 Data of second byte WA+2 Data of third byte The write operation is executed in the internal write cycle after the CS pin has gone low. CURRENT READ 10000000B [80H] MSB C7-C0 Transfers the contents of memory specified by the word address (WA) (current address) specified when the command is set, to the read data buffer. Each time 8 bits of data have been read from the SDA pin, the word address (WA) is incremented, and the corresponding memory contents are transferred to the data buffer. Executes data read starting from a set word address (WA) after the word address has been set. The difference from CURRENT READ is that this command sets a word address (WA) after it has been executed. After the word address has been set, this command performs the same operation as CURRENT READ. RANDOM READ 11000000B [C0H] MSB C7-C0 242 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-27. Communication Format of PD6252 (1) RANDOM WRITE WA input CS Command input Write data input (WA) (WA + 1) (WA + 2) WB flag output WA7 WA6 WA5 WA4 WA3 WA2 WA1 WA0 D7 D6 D5 D4 D3 D2 D1 D0 2nd byte 3rd byte 0 0 SDA SCL Internal WA SDA mode C7 C6 C5 C4 C3 C2 C1 C0 0 0 0 0 0 0 1st byte WA + 1 to WA + 3 CURRENT ADDRESS WA OUT IN WA retains input value until STP is Starts by making CS pin high detected, and is incremented each time when SCL pin is high 1 byte is written in the internal write (issuance of STA). cycle after STP has been detected. Data of 1st byte is written to WB flag is retained while eight memory addressed by WA. clocks are input to SCL pin. Write is executed by making CS in low with SCL pin high. (2) CURRENT READ WA is last written address + 1 and is retained (current address) (issuance of STP). IN Current address CS Command input Read data (WA) WB flag output 0 0 (WA + 1) (WA + 2) (WA + n) D0 D7 D6 D2 D1 D0 SDA SCL Internal WA SDA mode C7 C6 C5 C4 C3 C2 C1 C0 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 IN WA+1 WA+2 WA+n CURRENT ADDRESS = WA OUT OUT Operation ends by making CS pin high with SCL pin high. WA is last read address + 1 and retained (current address) (issuance of STP) WA + n + 1 (3) RANDOM READ CS WA input (WA) (WA+1) *** (WA+n) D1 D0 SDA SCL Internal WA SDA mode C7 C6 C5 C4 C3 C2 C1 C0 1 1 0 0 0 0 0 0 WB flag output WA7 WA6 WA5 WA4 WA3 WA2 WA1 WA0 D7 D6 D5 D4 D3 D2 D1 D0 D7 CURRENT ADDRESS IN OUT IN WB flag is retained while 8 clocks are input to SCL pin. WA OUT WA+1 WA+n WA + n + 1 Starts by making CS pin high with SCL pin high (issuance of STA). Contents of WA are read as data of first byte. Contents of WA+1, *** WA+n are sequentially read each time 1 byte has been read. Operation ends if CS pin is made low with SCL pin high (issuance of STP). WA is last read address + 1 and retained. 243 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Steps <1> through <5> below are the operating procedure of the PD6252. In this example, the number of data to be written or read per interface operation is fixed to 1 byte. If the PD6252 is in the write busy (WB) status when interfaced, the busy flag is set. <1> Make the CS pin (P32) high to start interfacing. <2> Transmit the write or read command. <3> Receive the data of WRITE BUSY. If interfacing the PD6252 is enabled, 00H is received. If a code other than 00H is received, it is judged that the PD6252 is in the WRITE BUSY status. In this case, communication is stopped. <4> Transfer the data corresponding to the command. <5> Make the CS pin (P32) low to end the communication. (1) Description of package TRNDAT : Transmit data storage area RCVDAT : Receive data storage area CMDDAT : Command data storage area BUSYFG : Busy status test flag CS6252 : CS pin (P32) of PD6252 Name WAADR TRNDAT RCVDAT CMDDAT Usage Stores word address (before start of transfer) Stores transmit data (before start of transfer) Stores receive data (after end of transfer) Stores command data (before start of transfer) Attribute SADDR Bytes 1 244 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Name BUSYFG Usage Sets WRITE BUSY status * Serial interface channel 0 * P32 * OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit * Setting of serial interface channel 0 CSIM0 = #10011011B ; Selects 2-wire serial I/O mode and SB1 pin ; Serial clock fXX/24 ; Makes SB1 latch high * TCL3 = #xxxx1001B * RELT = 1 Set the necessary data corresponding to the commands and call T3_6252. After execution returns from the subroutine, the busy flag (BUSYFG) is tested. If the busy flag is set, transfer is not executed. It is therefore necessary to execute transfer again. In the receive mode, the receive data is stored RCVDAT after execution has returned from the subroutine. 245 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (2) Example of use Sets each data to memory UNTIL: Not WRITE BUSY Clears busy flag Calls T3_6252 Loads receive data EXTRN EXTRN EXTBIT RWRITE,RREAD,CREAD WADAT,TRNDAT,RCVDAT,CMDDAT,T3_6252 BUSYFG,CS6252 ; Does not use divider circuit ; Sets 2-wire serial I/O mode and SB1 pin ; Sets SCK0 = 262 kHz ; Makes CS of PD6252 low OSMS=#00000001B CSIM0=#10011011B TCL3=#10011001B CLR1 SB0 CLR1 CS6252 CLR1 PM3.2 CMDDAT=A . . . . WADAT=A . . . . TRNDAT=A . . . . repeat CLR1 BUSYFG CALL !T3_6252 until_bit(!BUSYFG) . . . . A=RCVDAT 246 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart T3_6252 Clears busy flag Issues start bit Transfers command WHILE: waits for end of transfer (CSIIF0 = 0) Receives busy signal WHILE: waits for end of transfer (CSIIF0 = 0) IF: not WB status (SIO0 = 00H) THEN CASE: CMDDAT OF: RWRITE Transfers word address WHILE: waits for end of transfer Transfers data WHILE: waits for end of transfer BREAK OF: RREAD Transfers word address WHILE: waits for end of transfer OF: CREAD Receives data WHILE: waits for end of transfer Stores receive data to memory ELSE Sets busy status Sets BUSYFG Issues stop bit 247 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (4) Program list PUBLIC PUBLIC PUBLIC DSEG DS DS DS DS RWRITE,RREAD,CREAD WADAT,TRNDAT,RCVDAT,CMDDAT,T3_6252 BUSYFG,CS6252 SADDR 1 ; Word address storage area 1 ; Transmit data storage area 1 ; Receive data storage area 1 ; Command data storage area CSI_DAT WADAT: TRNDAT: RCVDAT: CMDDAT: CSI_FLG BSEG BUSYFG DBIT RWRITE RREAD CREAD CS6252 EQU EQU EQU EQU 00H 0C0H 080H 0FF03H.2 ; Sets busy status ; ; ; ; RANDOM WRITE mode RANDOM READ mode CURRENT READ mode 0FF03H=PORT3 CSI_SEG CSEG ;************************************* PD6252 (3-wire) communication ;* ;************************************* T3_6252: CLR1 BUSYFG SET1 CS6252 SI00=CMDDAT (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 SIO0=#0FFH while_bit(!CSIIF0) endw CLR1 CSIIF0 if(SIO0==#00H) switch (CMDDAT) case RWRITE: SIO0=WADAT (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 SIO0=TRNDAT (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 break case RREAD: SIO0=WADAT (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 case CREAD: SIO0=#0FFH while_bit(!CSIIF0) endw CLR1 CSIIF0 RCVDAT=SIO0 (A) ends ; Issues start bit ; Transfers command ; Waits for end of transfer ; Starts reception of busy signal ; Waits for end of transfer ; Busy check ; Transfers word address ; Waits for end of transfer ; Starts data transfer ; Waits for end of transfer ; Transfers word address ; Waits for end of transfer ; Starts data reception ; Waits for end of transfer ; Stores receive data 248 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE else SET1 BUSYFG endif CLR1 CS6252 RET ; Sets busy status 249 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.1.2 Communication in I2C bus mode In the 2-wire mode of the PD6252Note, two lines, serial clock (SCL) and data (SDA) lines are used for communication. This mode conforms to the communication format of I2C. Therefore, the I2C mode is selected when communicating with the PD6252 by using the PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, or PD78070AY. In the example shown in this section, the PD78054Y subseries is used. Note PD6252 is for maintenance use. Figure 8-28. Example of Connection between PD6252 and I2C Bus Mode PD78054Y SCL SDA0 (SDA1) PD6252 SCL SDA A2 = 0 A1 = 0 SCL SDA A2 = 0 A1 = 1 SCL SDA A2 = 1 A1 = 0 SCL SDA A2 = 1 A1 = 1 Figure 8-29 shows the communication format in which data is written to or read from the PD6252. 250 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-29. PD6252 Operation Timing (a) Transmission to PD6252 Start condition SDA SCL 1 0 1 0 A2 A1 WRITE 0 Stop condition ACK 0 ACK WA7 WA6 WA5 WA4 WA3 WA2 WA1 WA0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Slave address R/W command Word address Write data Write data (b) Reception from PD6252 (without word address specification) Start condition SDA SCL 1 0 1 0 A2 A1 READ 0 Stop condition 1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Slave address R/W command Read data Read data (c) Reception from PD6252 (with word address specification) Start condition SDA SCL 1 0 1 0 A2 A1 WRITE 0 Start condition 1 0 1 0 READ A2 A1 0 1 Stop condition 0 ACK WA7 WA6 WA5 WA4 WA3 WA2 WA1 WA0 ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 Slave address R/W command Word address Slave address R/W command Read data 251 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Steps <1> through <5> below are the communication procedure of the PD6252. In this example, the number of data to be written or read is fixed to 1 byte. If the master receives data in the I2C bus format, and if it has received the last data, the ACK signal is not output. Because the master does not output the ACK signal in this example, ACKE is always 0. <1> Set a start condition to start communication. Fall the data with the serial clock high. <2> Transmit the slave address value (bits 1 through 7) of the PD6252 and write (bit 0 = 0)/read (bit 0 = 1) select bit. 1 0 1 0 A2 A1 0 R/W Slave address 7-bit (bits 7 through 1) R/W selection 1 bit (bit 0) Remark A2 and A1 are set by external pins. <3> Transfer the data. * In transmission mode (i) Transmit the word address of the PD6252. (ii) Transmit the write data. * In reception mode Receive the read data. <4> Set an end condition to end the communication. Rise the data with the serial clock high. <5> Because a word address is specified only in the write mode, to read data by specifying an address, the address must be specified by once setting the write mode. If the PD6252 does not return the ACK signal during data transfer, communication is stopped. The start and end conditions are set by CLC when the serial clock is manipulated, and by RELT and CMDT when data is manipulated. 252 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (1) Description of package Name WAADR TRNDAT RCVDAT SLVADR Usage Stores word address (before start of transfer) Stores transmit data (before start of transfer) Stores receive data (after end of transfer) Stores slave address Attribute SADDR Bytes 1 Name BUSYFG WRCHG Usage Sets WRITE BUSY status Changes write mode to read mode ERRFG Sets error status 253 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE * OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit * Setting of serial interface channel 0 CSIM0 = #10011011B ; Selects 2-wire serial I/O mode and SB0 pin * TCL3 = #xxxx1000B * SINT = #00001011B ; Selects serial clock fXX/23 and 16 ; Generates interrupts at rising edge of 9th serial clock and sets clock line to high level Sets data Calls T2_6252 (IF: sets BUSYFG) Clears BUSYFG To busy processing (IF: sets ERRFG) Clears ERRFG To error processing EXTRN EXTBIT WAADR,TRNDAT,RCVDAT,SLVADR,T2_6252 BUSYFG,WRCHG,ERRFG SET1 SB0 OSMS=#00000001B CSIM0=#10011011B SINT=#00001011B TCL3=#10001000B SET1 RELT SET1 SCK0 CLR1 SB0 . . . . WAADR=A . . . . TRNDAT=A SLVADR=A CALL !T2_6252 if_bit(BUSYFG) CLR1 BUSYFG . . . . endif . . . . if|bit(ERRFG) CLR1 ERRFG . . . . ENDIF ; ; ; ; Does not use divider circuit Serial interface 2-wire, SB0 Sets I2C mode SCK = 32.7 kHz 254 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart T2_6252 IF: SCK0 = LOW THEN Sets busy status ELSE Sets BUSYFG Issues start bit Transmits slave address WHILE: waits for end of transfer (CSIIF0 = 0) IF: ACK signal not detected THEN Sets error status ELSE THEN Transmits word address of PD6252 WHILE: waits for end of transfer IF: ACK signal not detected THEN Sets error status ELSE Sets ERRFG IF: changes to read mode THEN WHILE: SCK0 = HIGH Outputs high level in order of data and clock Changes slave address to read mode GOTO STABIT ELSE Transmits data WHILE: waits for end of transfer IF: ACK signal not detected THEN Sets error status ELSE Receives data WHILE: waits for end of transfer Stores receive data to memory Outputs low level in order of clock and data Issues stop bit Sets ERRFG Sets ERRFG IF: transmit mode STABIT 255 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (4) Program list PUBLIC PUBLIC CSI_DAT WAADR: TRNDAT: RCVDAT: SLVADR: CSI_FLG BUSYFG WRCHG ERRFG SCK0 DSEG DS DS DS DS BSEG DBIT DBIT DBIT EQU P2.7 WAADR,TRNDAT,RCVDAT,SLVADR,T2_6252 BUSYFG,WRCHG,ERRFG SADDR 1 1 1 1 ; ; ; ; Word address storage area Transmit data storage area Receive data storage area Salve address storage area ; Sets busy status ; Changes mode ; Sets error status CSI_SEG CSEG ;************************************* PD6252 (2-wire) communication ;* ;************************************* T2_6252: if_bit(!CLD) SET1 BUSYFG else STABIT: SET1 CMDT NOP NOP NOP NOP NOP CLR1 CLC SIO0=SLVADR (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 if_bit(!ACKD) SET1 ERRFG elseif_bit(!SLVADR.0) SI00=WAADR (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 if_bit(!ACKD) SET1 ERRFG elseif_bit(WRCHG) while_bit(CLD) endw SET1 RELT SET1 CLC while_bit(!CLD) endw NOP NOP NOP NOP NOP NOP NOP NOP SET1 SLVADR.0 goto STABIT else ; Busy status ; Issues start bit ; Waits for start bit valid width ; Changes clock to low level ; Starts transmitting slave address ; Waits for end of transfer ; ACK signal not detected ; Transmission mode ; Starts transmitting word address ; Waits for end of transfer ; ACK signal not detected ; Checks high level of clock ; Waits for high level valid width of clock ; Changes to read mode address 256 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE SIO0=TRNDAT (A) while_bit(!CSIIF0) endw CLR1 CSIIF0 if_bit(!ACKD) SET1 ERRFG endif endif else SIO0=#0FFH while_bit(!CSIIF0) endw CLR1 CSIIF0 RCVDAT=SIO0 (A) endif while_bit(CLD) endw SET1 CMDT SET1 CLC while_bit(!CLD) endw NOP NOP NOP NOP NOP NOP NOP NOP SET1 RELT endif RET ; Starts transmitting data ; Waits for end of transfer ; ACK signal detected ; Starts data reception ; Waits for end of transfer ; Stores receive data ; Checks high level of clock ; Waits for high level valid width of clock ; Issues stop bit 257 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (5) Limitation when using I2C bus mode The following limitation applies when the PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY subseries, and PD78070AY are used. This section explains an example using the PD78054Y. * Limitation when the device is used as a slave device in the I2C bus mode Description: If the wake-up function is executed (by setting the WUP flag (bit 5 of serial operation mode register 0 (CSIM0) to 1) in the serial transfer statusNote, the data between other slave device and the master devices is checked as an address. If that data coincides with the slave address of the PD78054Y, therefore, the PD78054Y takes part in communication, destroying the communication data. Note The serial transfer status is the status from when the serial I/O shift register 0 (SIO0) has been written until the interrupt request flag (CSIIF0) is set to 1 by completion of serial transfer. Preventive measures: The above problem can be prevented by modifying the program. Before executing the wake-up function, execute the following program that clears the serial transfer status. When executing the wake-up function, do not execute an instruction that writes data to SIO0. Even if such an instruction is executed, data can be received when the wake-up function is executed. This program is to clear the serial transfer status. To clear the serial transfer status, serial interface channel 0 must be stopped (by clearing the CSIE0 flag (bit 7 of the serial operation mode register (CSIM0) to 0). If the serial interface channel 0 is stopped in the I2C bus mode, however, the SCL pin outputs a high level and the SDA0 (SDA1) pin outputs a low level, affecting communication on the I2C bus. Therefore, this program allows the SCL and SDA0 (SDA1) pin to go into a highimpedance state to prevent the I2C bus from being affected. Note that, in this example, the serial data input/output pin is SDA0 (/P25). If SDA1 (/P26) is used as the serial data input/output pin, take P2.5 and PM2.5 in the program as P2.6 and PM2.6. 258 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE * Example of program that clears serial transfer status SET1 SET1 SET1 CLR1 SET1 SET1 CLR1 CLR1 CLR1 P2.5 PM2.5 PM2.7 CSIE0 CSIE0 RELT PM2.7 P2.5 PM2.5 ; <1> ; <2> ; <3> ; <4> ; <5> ; <6> ; <7> ; <8> ; <9> <1> When the I2C bus mode is restored by instruction <5>, the SDA0 pin does not output a low level. The output of the SDA0 pin goes into a high-impedance state. <2> The P25(/SDA0) pin is set in the input mode to prevent the SDA0 line from being affected when the port mode is set by instruction <4>. The P25 pin is set in the input mode when instruction <2> is executed. <3> The P27 (/SCL) pin is set in the input mode to prevent the SCL line from being affected when the port mode is set by instruction <4>. The P27 pin is set in the input mode when instruction <3> is executed. <4> The I2C bus mode is changed to the port mode. <5> The port mode is changed to the I2C bus mode. <6> Instruction <8> prevents the SDA0 pin from outputting a low level. <7> The P27 pin is set in the output mode because it must be in the output mode in the I2C bus mode. <8> The output latch of the P25 pin is cleared to 0 because it must be cleared to 0 in the I2C bus mode. <9> The P25 pin is set in the output mode because it must be in the output mode in the I2C bus mode. Remark RELT: Bit 0 of serial bus interface control register (SBIC) 259 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.2 Interface with OSD LSI (PD6451A) The OSD (On Screen Display) LSI PD6451A displays the program information of a VCR and TV channels on a display when used in combination with a microcontroller. The PD6451A is interface with four lines: DATA, CLK, STB, and BUSY. In the example shown in this section, the PD78054 subseries is used to interface the PD6451A. Figure 8-30. Example of Connecting PD6451A PD78054 SCK1 SO1 STB BUSY PD6451A CLK DATA STB BUSY RGB Display RGB Figure 8-31. Communication Format of PD6451A SCK1 SO1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 STB BUSY The strobe signal (STB) is output and busy signal (BUSY) is tested automatically by the serial interface channel 1 of the 78K/0 series to establish handshaking with and to interface the PD6451A. To match the communication format of the PD6451A, the PD78054 subseries is set in a mode in which output of the strobe signal and input of the busy signal (high active) are enabled. By setting the transmit data (32 bytes MAX) in a buffer area (FAC0H through FADFH) and the number of transmit data to the automatic data transmit/receive address pointer (ADTP), you can automatically transmit plural data successively. 260 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (1) Description of package Name DTVAL Usage Stores number of transmit data Attribute SADDR Bytes 1 261 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (2) Example of use Sets data to buffer RAM Sets number of data to be transmitted to DTVAL Calls TR6451 WHILE: waits for end of transfer EXTRN SCK1 EQU TR6451,DTVAL P2.2 . . . . OSMS=#00000001B P2=#00000100B PM2=#11110001B CSIM1=#10100011B TCL3=#10011001B ADTC=#00000110B ADTI=#00000000B . . . . DE=#TABLE1 HL=#0FAC0H B=32 while(B>#0) B-- [HL+B]=[DE] (A) DE++ endw DATVAL=#32 CALL !TR6451 while_bit(TRF) endw ; Does not use divider circuit ; ; ; ; Sets automatic transfer/reception function SCK1 = 262 kHz Enable strobe and busy signals Interval time of data transfer ; Sets table reference address of transmit data ; Sets first address of buffer RAM ; Sets number of data to be transmitted ; Transfers transmit data to buffer RAM ; Sets number of data to be transmitted ; Waits for end of transfer 262 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE TABLE1: DB DB DB DB DB DB DB DB DB DB 11111111B 01000000B 11000000B 10000000B 11111100B 11101001B 10001100B 11011011B 10010101B 10100000B ; ; ; ; ; ; Power-ON reset, command 1 Vertical address 0 Horizontal address 0 Character size Command 0 Turns LC transmission ON, blinking OFF, display ON ; Turns blinking ON. Character: red ; Color specification, background filled in cyan ; Number of display lines: 5 ; Number of display digits: 0 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 07H 08H 1BH 6DH 00H 10H 11H 20H 20H 1CH 19H 13H 11H 24H 19H 00H 1EH 10H 1EH 00H 24H 15H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 7 8 K / 0 A P P L I C A T I O N N O T E Remark For the command and data of the output table data, refer to PD6451A Data Sheet (Document No. IC2337). 263 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart TR6451 Sets (number of data to be transmitted - 1) to ADTP Sets status before transfer Starts transfer (4) Program list PUBLIC CSI_DAT DSEG DTVAL: DS TR6451,DTVAL SADDR 1 ; Number of data setting area CSI_SEG CSEG ;************************************* PD6451A communication ;* ;************************************* TR6451: A=DTVAL A-- ADTP=A SIO1=#0FFH RET ; Sets number of data ; Starts transfer 264 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.3 Interface in SBI Mode The 78K/0 series has an SBI mode conforming to NEC serial bus format. In this mode, one master CPU can communicate with two or more slave CPUs by using two lines: clock and data. In the example shown in this section, the PD78054 subseries is used. Figure 8-32 shows an example of connection to use the SBI mode, and Figure 8-33 shows the communication format. Figure 8-32. Example of Connection in SBI Mode VDD PD78054 master SB0 SCK0 PD78054 slave SB0 SCK0 Slave CPU SB SCK Slave CPU SB SCK 265 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-33. Communication Format in SBI Mode (a) Address transmission SCK0 SB0 Sets Sets RELD CMDD A7 A6 A5 A4 A3 A2 A1 A0 (b) Command transmission SCK0 SB0 Sets CMDD C7 C6 C5 C4 C3 C2 C1 C0 (c) Data transmission/reception SCK0 SB0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Sets ACKD Table 8-9. Signals in SBI Mode Signal Name Address Command Data Clock ACK BUSY Output by: Master Master Master/slave Master Receiver Slave sideNote Selects slave device Command to slave device Data to be processed by slave or master Serial data transmission/reception synchronization signal Reception acknowledge signal Busy status Meaning Note This signal is output by the receiver side during normal operation. However, it is output by the master CPU in case of an error such as time out. 266 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.3.1 Application as master CPU When the PD78054 subseries is used as a master CPU, it performs processing (a) through (d) below with respect to slave CPUs. (a) Address transmission (b) Command transmission (c) Data transmission (d) Data reception While the above processing is performed, errors <1> and <2> below are checked. <1> Time out processing If the master CPU transmits data and a slave does not return the ACK signal within a specific time (in this example, before the watch interrupt request occurs five times), the master judges that an error has occurred. The master CPU then outputs an ACK signal and terminates the processing. Figure 8-34. ACK Signal in Case of Time out End of transfer Master output SB0 ACK (time out) INTTM3 (ACKD test) <2> Testing bus line The master CPU tests whether data has been correctly output to the bus line by setting the transmit data to the serial I/O shift register 0 (SIO0) and the slave address register (SVA). Because the data on the bus line is received by SIO0, it confirms that the data has been output normally by testing bit 6 (COI) of the serial operating mode register 0 (CSIM0) (that is set when SIO0 coincides with SVA) at the end of transfer. Figure 8-35. Testing Bus Line SIO0 = 0FH 0 0 0 0 1 1 1 1 SB0 = 07H 0 0 0 0 0 1 1 1 In Figure 8-35, the values of SIO0 and SVA do not coincide (SIO0 = 07H and SVA = 0FH). Consequently, COI = 0, and an error has occurred on the bus line. 267 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (1) Description of package Name TR_MODE ACKCT TRNDAT RCVDAT Usage Stores transfer mode select value Time out counter Stores transmit data Stores receive data Attribute SADDR Bytes 1 Name RCVFLG BUSYFG ERRORF ACKWFG Sets reception mode Sets busy status Sets error status Sets ACK signal wait status Usage 268 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE * Serial interface channel 0 * Watch timer * OSMS=#00000001B ; Oscillation mode select register: does not use divider circuit * Sets serial interface channel 0 CSIM0=#10010011B ; Selects SBI mode and SB1 pin ; Serial clock: fXX/24 ; Makes SO0 latch high ; Makes P27 output latch high ; Watch timer interval: 1.95 ms * * * * * TCL3=#xxxx1001B RELT=1 P27=1 TMC2=#00100110B Enables watch timer interrupt 269 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (2) Example of use Sets transfer mode Sets transmit data Calls M_TRANS IF: error occurs Error processing EXTRN EXTRN EXTBIT SCK0 SB1 M_TRANS,TR_MODE,TRADR,TRCMD,TRDAT,RCDAT TRNDAT,RCVDAT ERRORF EQU EQU P2.7 P2.5 . . . . OSMS=#00000001B SET1 SB1 CSIM0=#10010111B TCL3=#10011001B TMC2=#00100110B CLR1 BSYE SET1 RELT SET1 SCK0 CLR1 SB1 CLR1 CSIMK0 CLR1 TMMK3 EI . . . . TR_MODE=#TRADR TRNDAT=#5AH CALL !M_TRANS if_bit(ERRORF) Error processing endif ; Does not use divider circuit ; ; ; ; ; Operates in SBI mode SCK0 = 262 kHz Sets interval of watch timer to 1.95 ms Disables output of busy signal Sets output latch ; Enables serial interface channel 0 interrupt ; Enables watch timer interrupt ; Enables master interrupt 270 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart M_TRANS CASE: TR_MODE OF: TRADR WHILE: SB0 = LOW WHILE: SCK0 = LOW Outputs command signal Outputs bus release signal OF: TRCMD WHILE: SB0 = LOW WHILE: SCK0 = LOW Outputs command signal OF: TRDAT Sets transmission mode Clears RCVFLG BREAK OF: RCDAT Sets reception mode Sets RCVFLG Sets output off data (FFH) of bus line BREAK Sets transmission status Sets BUSYFG Sets transmit data to SIO0 and SVA WHILE: transfer in progress (sets BUSYFG) Stores data of SIO0 to RCVDAT IF: transmission mode THEN IF: error occurs in bus line THEN Sets error status Sets ERRORF 271 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE INTCSI0 Selects register bank 0 IF: transmission mode THEN IF: ACK signal not received THEN Sets ACK wait status Sets ACKWFG ELSE Clears busy status Clears BUSYFG Clears error status ELSE Clears ERRORF Outputs ACK signal Clears BUSYFG and ERRORF INTTM3 Selects register bank 0 IF: ACK wait status THEN IF: ACK received THEN Clears ACK wait status Clears ACKWFG Clears busy status Clears BUSYFG ELSE IF: time out THEN Time out error processing Clears ACK wait status Clears ACKWFG Clears busy status Clears BUSYFG 272 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (4) Program list PUBLIC PUBLIC VECSI0 VETM3 CSEG DW CSEG DW M_TRANS,TR_MODE,TRADR,TRCMD,TRDAT,RCDAT TRNDAT,RCVDAT,ERRORF AT 14H INTCSI0 AT 1EH INTTM3 SADDR 1 1 1 1 ; Sets vector address of serial interface channel 0 ; Sets vector address of watch timer SBI_DAT DSEG TRNDAT: DS RCVDAT: DS TR_MODE:DS ACKCT: DS SBI_FLG RCVFLG BUSYFG ERRORF ACKWFG SB0 SCK0 TRADR TRCMD TRDAT RCDAT BSEG DBIT DBIT DBIT DBIT EQU EQU EQU EQU EQU EQU ; ; ; ; Transmit data Receive data Sets transfer mode ACK time out count ; ; ; ; Sets reception mode Transfer status Error display ACK wait status P2.5 P2.7 1 2 3 4 ; ; ; ; Selects Selects Selects Selects address transmission mode command transmission mode data transmission mode data reception mode 273 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE ;******************************************* SBI data transfer processing ;* ;******************************************* SBI_SEG CSEG M_TRANS: switch(TR_MODE) case TRADR: SET1 PM2.5 while_bit(!SB0) CLR1 PM2.5 endw while_bit(!SCK0) endw SET1 CMDT NOP SET1 RELT A=#TRCMD case TRCMD: SET1 PM2.5 while_bit(!SB0) CLR1 PM2.5 endw while_bit(!SCK0) endw SET1 CMDT A=#TRDAT case TRDAT: CLR1 RCVFLG A=TRNDAT break case RCDAT: SET1 RCVFLG MOV A,#0FFH break ends SET1 SVA=A SIO0=A BUSYFG ; SB0 = high? ; SCK = high? ; Outputs command signal ; Wait ; Outputs bus release signal ; SB0 = high? ; SCK = high? ; Outputs command signal ; Sets transmission mode ; Sets transmit data ; Sets reception mode ; Turns off receive buffer ; Sets transfer status ; Tests bus line ; Starts transfer ; Transfer in progress ; ; ; ; Stores receive data Transmission mode Bus line output abnormal Sets error status while_bit(BUSYFG) endw RCVDAT=SIO0 (A) if_bit(!RCVFLG) if_bit(!COI) SET1 ERRORF endif endif RET 274 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE ;*************************************** INTCSI0 interrupt processing ;* ;*************************************** CSI_SEG CSEG INTCSI0: SEL RB0 if_bit(!RCVFLG) if_bit(!ACKD) ACKCT=#5 SET1 ACKWFG else CLR1 BUSYFG CLR1 ERRORF endif else SET1 ACKT CLR1 BUSYFG CLR1 ERRORF endif RET ;*************************************** Time out processing ;* ;*************************************** TM3_SEG CSEG INTTM3: SEL RB0 if_bit(ACKWFG) if_bit(ACKD) CLR1 ACKWFG CLR1 BUSYFG else ACKCT-if(ACKCT==#0) SET1 ACKT SET1 ERRORF CLR1 ACKWFG CLR1 BUSYFG endif endif endif ; Transmission mode ; Acknowledge signal not received ; Sets acknowledge signal wait status ; Clears busy status ; Clears error status ; Outputs acknowledge signal ; Clears busy status ; Clears error status ; ; ; ; Acknowledge signal wait status? Acknowledge signal received? Clears acknowledge signal wait status Clears busy status ; Time out? ; Time out error processing ; Clears acknowledge signal wait status ; Clears busy status 275 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.3.2 Application as slave CPU A slave CPU receives addresses, commands, and data from the master CPU and transmits data to the master CPU. In the example shown in this section, addresses are received by using the wake-up function. This function is to generate an interrupt only when the address value transmitted by the master to the slave coincides with the value set to the slave address register (SVA) of the slave in the SBI mode. Therefore, only the slave CPU selected by the master CPU generates INTCSI0, and the slave CPUs not selected operates without generating an inadvertent interrupt request. The slave CPU clears the wake-up function when it has been selected by the master (the interrupt request signal is generated at the end of transmission), and interfaces with the master CPU. Addresses, commands, and data being transmitted are identified by using bits 2 and 3 (RELD and CMDD) of the serial bus interface control register (SB IC). Because the slave CPU is not automatically placed in the unselect status, a program that returns the slave CPU to the unselect status must be prepared by processing commands between the master and CPU. (1) Description of package Name RCVDAT Stores receive data Usage Attribute SADDR Bytes 1 Name RCVFLG Sets reception mode Usage * Serial interface channel 0 * Setting of serial interface channel 0 CSIM0=#10010011B; Sets SBI mode, SBI pin, and wake-up mode, and inputs serial clock from external source Outputs synchronous busy signal Makes SO0 latch high Slave address * * * * BYSE=1 RELT=1 SVA=#SLVADR; Enables serial interface channel 0 interrupt 276 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE * Identifies address/command/data * Outputs ACK signal * Stores receive data to RCVDAT (2) Example of use EXTRN EXTBIT RCVDAT RCVFLG SLVADR EQU 5AH SB1 EQU P2.5 . . . . SET1 SB1 CSIM0=#10110100B SET1 RELT SET1 BSYE SVA=#SLVADR SIO0=#0FFH CLR1 SB1 CLR1 CSIMK0 EI ; ; ; ; ; Inputs external clock, sets SB1 pin, and selects wake-up mode Sets output latch to high level Sets busy automatic output Sets slave address Serial transfer start command ; Enables serial interface channel 0 interrupt ; Enables master interrupt (3) SPD chart INTCSI0 Selects register bank 0 IF: address received THEN Clears wake-up mode Outputs ACK signal Address coincidence processing ELSE IF: command received THEN Command reception processing Outputs ACK signal ELSE IF: reception mode THEN Data reception processing Outputs ACK signal ELSE Data transmission processing Stores SIO0 data to memory 277 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (4) Program list VECSI0 CSEG DW AT 14H INTCSI0 SADDR 1 ; Sets vector address of serial interface channel 0 ; Receive data storage area SCI_DAT DSEG RCVDAT: DS CSI_FLG BSEG RCVFLG DBIT ; Sets reception mode CSI_SEG CSEG ;*************************************** INTCSI0 interrupt processing ;* ;*************************************** INTCSI0: SEL RB0 if_bit(RELD) CLR1 WUP SET1 ACKT ; User processing (address reception) ;*************************************** elseif_bit(CMDD) User processing (command reception) SET1 else ACKT ; To address reception ; Clears wake-up mode ; Outputs acknowledge signal ; To command reception ; ; Outputs acknowledge signal if_bit(RCVFLG) User processing (data reception processing) SET1 ACKT ; Outputs acknowledge signal else ; User processing (data transmission processing) endif ;*************************************** endif RCVDAT=SIO0 (A) ; RETI 278 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.4 Interface in 3-Wire Serial I/O Mode In this section, examples of communication between the master and a slave by using the 3-wire serial I/O mode (serial clock, data input, data output) of the serial channel 0 of the 78K/0 series are shown. In these examples, one extra busy signal is used as a handshake signal for simultaneous transmission/reception between the master and slave. This busy signal is active-low and is output by the slave. The data is 8 bits long and transmitted with the MSB first. In the examples in this section, the PD78054 subseries is used. Figure 8-36. Example of Connection in 3-Wire Serial I/O Mode Master SCK0 SI0 SO0 BUSY SCK0 SO0 SI0 BUSY Slave Figure 8-37. Communication Format in 3-Wire Serial I/O Mode BUSY SCK0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 279 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.4.1 Application as master CPU The serial clock is set to fXX/24, and communication is executed in synchronization with this serial clock between the master and slave CPUs. The master CPU starts transmission after it has set the transmit data. If the slave CPU is busy (when the busy signal is low), however, the master does not transmit data and sets the busy flag (BUSYFG). (1) Description of package Name TDATA RDATA Stores transmit data Stores receive data Usage Attribute SADDR Bytes 1 Name TREND BUSYFG Usage Sets transfer end status Sets busy status 280 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Sets transmit data UNTIL: BUSYFG cleared Clears BUSYFG Calls TRANS WHILE: TREND cleared Loads receive data EXTRN EXTBIT SCK0 TDATA,RDATA,TRANS TREND,BUSYFG,BUSY EQU P2.7 . . . . OSMS=#00000001B CSIM0=#10000011B TCL3=#10011001B SET1 SCK0 SET1 PM3.3 CLR1 CSIMK0 EI . . . . TDATA=A repeat CLR1 BUSYFG CALL !TRANS until_bit(!BUSYFG) while_bit(!TREND) endw A=RDATA ; Does not use divider circuit ; Sets 3-wire serial I/O mode with MSB first ; Sets SCK0 = 262 kHz ; Sets P3.3 input mode ; Enables serial interface channel 0 ; Sets transmit data ; Busy test ; Ends transfer ; Loads receive data 281 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart TRANS IF: transfer enabled THEN Sets transmit data to SIO0 ELSE Sets busy status Sets BUSYFG INTCSI0 Selects register bank 0 Stores data of SIO0 to memory Sets transfer end status Sets TREND (4) Program list PUBLIC CSEG DW EQU TRANS,RDATA,TDATA,BUSY,TREND,BUSYFG AT 14H INTCSI0 ; Sets vector address of serial interface channel 0 0FF03H.3 SADDR 1 1 ; 0FF03H = PORT3 VECSI0 BUSY CSI_DAT DSEG RDATA: DS TDATA: DS CSI_FLG BSEG TREND DBIT BUSYFG DBIT CSI_SEG CSEG ; Receive data storage area ; Transmit data storage area ; Sets transfer end status ; Sets busy status ;************************************** ;:* INTCSI0 interrupt processing ;************************************** INTCSI0: SEL RB0 RDATA=SIO0 (A) SET1 TREND RETI ;************************************** ;* 3-wire (master) ;************************************** TRANS: if_bit(BUSY) SIO0=TDATA (A) else SET1 BUSYFG endif RET ; Stores receive data ; Sets transfer end status ; Enables transfer ; Sets transmit data ; Sets busy status 282 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.4.2 Application as slave CPU In this example, a slave CPU simultaneously transmits and receives 8-bit data in synchronization with the serial clock from the master CPU. The busy signal output by the slave CPU is low (busy status) while the transmit data is prepared. This busy signal is cleared (high level) when the transmit data is set (CALL !TRANS), and is output (low level) when interrupt INTCSI0 occurs at the end of transfer. Therefore, the busy status remains after the end of transfer until the data is set. Figure 8-38. Output of Busy Signal Waits for Transmission transmission in progress Transmit data being prepared BUSY Sets transmit data INTCSI0 Sets transmit data (1) Description of package Name TDATA RDATA Stores transmit data Stores receive data Usage Attribute SADDR Bytes 1 Name TREND Usage Sets transfer end status 283 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Sets transmit data Calls TRANS WHILE: TREND cleared Loads receive data ; Sets 3-wire serial I/O mode with MSB first, and inputs external clock ; P33 output mode EXTRN EXTBIT . . . . TDATA,RDATA,TRANS TREND,BUSY CSIM0=#10000000B CLR1 BUSY CLR1 PM3.3 CLR1 CSIMK0 EI . . . . TDATA=A CALL !TRANS while_bit(!TREND) endw A=RDATA ; ; ; ; Sets 3-wire I/O mode with MSB first Busy status P3.3 output mode Enables serial interface channel 0 ; Sets transmit data ; Ends transfer ; Loads receive data 284 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart TRANS Sets transmit data to SIO0 Clears busy signal INTCSI0 Selects register bank 0 Outputs busy signal Stores SIO0 data to memory Sets transfer end status (4) Program list PUBLIC PUBLIC CSEG DW RDATA,TDATA,BUSY,TREND,BUSYFG TRANS AT 14H INTCSI0 SADDR 1 1 VECSI0 ; Sets vector address of serial interface channel 0 CSI_DAT DSEG RDATA: DS TRADA: DS CSI_FLG BSEG TREND DBIT BUSYFG DBIT BUSY EQU ; Stores receive data ; Stores transmit data ; Sets transfer end status ; Sets busy status 0FF03H.3 ; 0FF03H = PORT3 CSI_SEG CSE ;************************************** ;* INTCSI0 interrupt processing ;************************************** INTCSI0: SEL RB0 CLR1 BUSY RDATA=SI00 (A) SET1 TREND RETI ;************************************** ;* 3-wire (slave) ;************************************** TRANS: SIO0=TDATA (A) SET1 BUSY RET ; Sets busy status ; Stores receive data ; Sets transfer end status ; Sets transmit data ; Clears busy status 285 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE 8.5 Interface in Asynchronous Serial Interface (UART) Mode Serial interface channel 2 has two modes: asynchronous serial interface (hereafter referred to as "UART") and 3-wire serial I/O modes. Serial interface channel 2 is set by the following registgers: * * * * * Serial operating mode register 2 (CSIM2) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Oscillation mode select register (OSMS) UART using serial interface channel 2 is briefly described below. The UART mode of serial interface channel 2 is to transmit or receive 1-byte data following a start bit and can perform full-duplex operation. The operations of UART communication are described below. (a) Communication format One data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit. The character bit length, parity, and stop bit length in one data frame are specified by using the asynchronous serial interface mode register (ASIM). (b) Setting of baud rate A UART dedicated baud rate generator is provided that can set a wide range of baud rates. A baud rate can also be defined by dividing the clock input to the ASCK pin. The transmit/receive clock for the band rate is generated by dividing the main system clock. The baud rate generated from the main system clock can be calculated by the following expression. Table 8-10 shows the relations between the main system clock and baud rate (at fx = 4.19 MHz). [Baud rate] = fXX 2n x (k + 16) Remarks 1. fXX: main system clock frequency (fX or fX/2) 2. fX : main system clock oscillation frequency 3. n : value set by TPS0-TPS3 (bits 4-7 of the baud rate generator control register (BRGC) (1 n 11) 4. k : value set by MDL0-MDL3 (bits 0-3 of BRGC) (0 k 14) [Hz] 286 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Table 8-10. Relations between Main System Clock and Baud Rate (at fX = 4.19 MHz) MCS = 1 Baud rate (bps) Set value of BRGC 75 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 76800 0BH 03H EBH DBH CBH BBH ABH 9BH 8BH 7BH 71H 6BH 5BH Error (%) 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 1.14 Set value of BRGC EBH E3H DBH CBH BBH ABH 9BH 8BH 7BH 6BH 61H 5BH - Error (%) 1.14 -2.01 1.1.4 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 - MCS = 0 Remark MCS: bit 0 of the oscillation mode select register (OSMS) (c) Transmission Transmission is started when transmit data has been written to the transmit shift register (TXS). The start bit and parity bit are automatically appended. (d) Reception Reception is enabled when bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set to 1, and the data input to the RxD pin is sampled. When reception of one frame of data has been completed, the receive data in the shift register is transferred to the receive buffer register (RXB) and a receive end interrupt request (INTSR) occurs. (e) Receive error During reception, three types of errors may occur: parity error, framing error, and overrun error. If the error flag of the asynchronous serial interface status register (ASIS) is set as a result of data reception, a receive error interrupt (INTSER) occurs. By reading the contents of ASIS in the receive error interrupt processing (INTSER), which error has occurred can be identified. The contents of ASIS are reset (0) by either reading the receive buffer register (RXB) or receiving the next data. (if the next data includes an error, that error flag is set). Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are reset to 0 when the receive buffer register (RXB) is read or the next data is received. To determine the nature of the error, be sure to read ASIS before reading RXB. 2. Be sure to read the receive buffer register (RXB) when a reception error has occurred. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 287 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE During communication, transmission and reception with a terminal is performed and RTS and CTS are controlled for handshaking. The communication protocol is shown below. * * * * * * Baud rate: 9600 bps No parity bit Stop bit: 2 bits LSB first CTS input pin: P31 RTS output pin: P32 When transmission is started, the end of the previous transmission (in which case the transmission end interrupt request flag (STIF) is set to 1) is checked, and transmission is executed if the CTS input status is ready ("L"). During reception, the busy signal ("H") is output to the RTS output pin when a reception end interrupt request (INTSR) occurs. "L" is output to the RTS output pin when reception is enabled. A receive error interrupt request (INTSER) occurs if a receive error (parity error, framing error, or overrun error) occurs, and the error flag is set. Figure 8-39 shows a communication block diagram, and Figures 8-40 and 8-41 show the transmission/reception format. Figure 8-39. Communication Block Diagram PD78054 Terminal TXD TXD RXD RXD CTS input CTS input RTS output RTS output 288 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-40. Communication Format Reception at reception side OK CTS input pin P31 Data output TXD Transmission end interrupt request INTST Start bit Communication start timing D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Figure 8-41. Reception Format RTS output pin P32 Data input RXD Receive end interrupt request INTSR Receive error interrupt request INTSER Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit 289 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (1) Description of package Name SOSHIN JUSHIN Usage Transmit data storage area Receive data storage area Attribute SADDR SADDR Bytes 1 1 : Bank 3, A : Bank 3, A Name F_TUSHIN F_BUSY Usage Set at end of reception Set if transmission cannot be started by CTS input pin; cleared if transmission can be started Set if receive error occurs F_ERR 290 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE * Serial interface channel 2 (UART mode) * OSMS=#00000001B * CLR1 P3.2 PM3=#xxxx10xB ; Oscillation mode select register: does not use divider circuit ; P31 = CTS input, P32 = RTS output ; Sets baud rate to 9600 bps (error: 1.14%) ; Sets 0 to serial operation mode register 2 when UART is used ; Sets asynchronous serial interface mode register ; Clears reception end receive error interrupt request flags ; Sets transmission end interrupt request flag (to end transmission) ; Enables reception end and receive error interrupts * * * * BRGC=#10001011B CSIM2=#00000000B ASIM=#11001101B CLR1 SRIF CLR1 SERIF * SET1 STIF * CLR1 SRMK CLR1 SERMK Caution Before starting transmission, check the transmission end interrupt request flag (STIF) so that transmission is not executed during transmission. Therefore, set the transmission end interrupt request flag (STIF) after reset and start. Remark To use the transmission end interrupt (to generate the interrupt request), use an additional flag. Set the additional flag as the initial setting. Clear the flag at the start of transmission, and set it in the interrupt processing. 291 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (2) Example of use EXTRN S_SOSHIN EXTRN SOSHIN,JUSHIN EXTBIT F_TUSHIN,F_ERR,F_BUSY ; RTS_0 EQU P3.2 ; OSMS=#00000001B CLR1 RTS_0 PM3=#11111011B BRGC=#10001011B CSIM2=#00000000B ASIM=#11001101B CLR1 CLR1 SET1 ; CLR1 CLR1 EI . . . . if_bit(transmission request) ; Sets transmission request flag? SOSHIN=A ; Stores transmit data CALL !S_SOSHIN ; Calls transmit routine endif if_bit(F_BUSY) ; End of transmission? . Communication busy processing ; . endif . . if_bit(F_TUSHIN) CLR1 F_TUSHIN A=JUSHIN . Reception processing . CLR1 endif . . RTS_0 ; Sets reception end flag? ; Clears reception end flag ; Reads receive data ; ; RTS output pin "L" (ready status) ; ; ; RTS output port ; ; ; ; ; ; ; ; ; ; ; ; ; ; Does not use divider circuit P31 = CTS input, P32 = RTS output 9600 bps (error: 1.41%) Initial setting when UART is used Enables receive error interrupt. Stop bit: 2 bits Transmit data: 8 bits. No parity. Enables reception and transmission. Clears receive error interrupt request flag Clears reception end interrupt request flag Sets transmit end interrupt request flag Ends transmission Enables receive error interrupt Enables reception end interrupt SERIF SRIF STIF SERMK SRMK if_bit(F_ERR) CLR1 F_ERR . Receive error processing . endif . . ; Receive error occurs? ; ; ; 292 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (3) SPD chart S_SOSHIN THEN (if: previous transmission ends ?) (if: transmission enabled ?) THEN Clears transmit busy flag Clears transmit end interrupt request flag TXS transmit data ELSE Sets transmit busy flag ELSE Sets transmit busy flag INTSR Selects register bank 3 RTS output pin "H" (sets busy status) JUSHIN RXB (loads receive data) Sets reception end flag INTSER Selects register bank 3 A RXB (loads receive error data) Sets receive error flag 293 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (4) Program list PUBLIC PUBLIC PUBLIC ; VESR VESER S_SOSHIN SOSHIN,JUSHIN F_TUSHIN,F_ERR,F_BUSY CSEG DW CSEG DW AT 1AH INTSR AT 18H INTSER ; RTS output port ; CTS input port ; RTS_0 EQU P3.2 CTS_I EQU P3.1 ; UARTRAM DSEG SADDR SOSHIN: DS 1 JUSHIN: DS 1 ; UARTFLG BSEG F_TUSHIN DBIT F_BUSY DBIT F_ERR DBIT ; ;************************************ ; Transmission routine ;************************************ UARTPR0 CSEG S_SOSHIN: if_bit(STIF) if_bit(!CTS_I) CLR1 STIF TXS=SOSHIN (A) CLR1 F_BUSY else SET1 F_BUSY endif else SET1 F_BUSY endif RET ;************************************ ; Reception end routine ;************************************ INTSR: SEL RB3 SET1 RTS_0 JUSHIN=RXB (A) SET1 F_TUSHIN RETI ;************************************ ; Reception error routine ;************************************ INTSER: SEL RB3 A=RXB SET1 F_ERR RETI END ; Transmit data storage area ; Receive data storage area ; Reception end flag ; Communication busy flag ; Reception error flag ; Previous transmission end? ; Enables transmission? ; Clears transmit end interrupt request flag ; Stores transmit data ; Clears transmit busy flag ; ; Disables transmission sets transmission busy flag ; ; ; ; ; ; RTS H ; Loads receive data ; Sets reception end flag ; ; Selects bank 3 ; Reads error data ; Sets receive error flag ; 294 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE (f) Limitation when using UART mode In the UART mode, the reception completion interrupt (INTSR) occurs a certain time after the reception error interrupt (INTSER) has occurred and cleared. As a result, the following phenomenon may take place. * Description If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the reception completion interrupt (INTSR) does not occur when a reception error occurs. If the receive buffer register (RXB) is read at certain timing (a in Figure 8-42) during reception error interrupt (INTSER) processing, the internal error flag is cleared to 0. Therefore, it is judged that a reception error has not occurred, and INTSR, which should not occur, occurs. Figure 8-42 illustrates this operation. Figure 8-42. Timing of Reception Completion Interrupt (when ISRM = 1) fSCK INTSER (when framing overrun error occurs) Error flag (internal flag) Cleared when RXB is read a INTSR Interrupt routine of CPU Reads RXB It is judged that receive error has not occurred, and INTSR occurs. Remark ISRM : Bit 1 of asynchronous serial interface mode register (ASIM) fSCK : Source clock of 5-bit counter of baud rate generator RXB : Receive buffer register To prevent this phenomenon, take the following measures: * Preventive measures * In case of framing error or overrun error Disable the receive buffer register (RXB) from being read for a certain period (T2 in Figure 8-43) after the receive error interrupt (INTSER) has occurred. * In case of parity error Disable the receive buffer register (RXB) from being read for a certain period (T1 + T2 in Figure 8-43) after the reception error interrupt (INTSER) has occurred. 295 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE Figure 8-43. Receive Buffer Register Reading Disabled Period RxD (input) START D0 D1 D2 D6 D7 Parity STOP INTSR INTSER (when framing or overrun error occurs) INTSER (when parity error occurs) T1 T2 T1: Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate) T2: Time of two source clocks (fSCK) of 5-bit counter selected by BRGC * Example of preventive measures An example of preventive measures is shown below. [Condition] fX = 5.0 MHz Processor clock control register (PCC) = 00H Oscillation mode select register (OSMS) = 01H Baud rate generator control register (BRGC) = 80H (2400 bps is selected as baud rate) tCY = 0.4 s (tCY = 0.2 s) T1 = 1 2400 = 833.4 s T2 = 12.8 x 2 = 25.6 s T1 + T2 tCY = 4295 (clocks) 296 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE [Example] Main processing UART receive error interrupt (INTSER) processing EI INTSER occurs 7 CPU clocks (min.) (time from interrupt request to processing) Instructions of 4288 CPU clocks (MIN.) are necessary MOV A, RXB RETI 297 [MEMO] 298 CHAPTER 9 APPLICATIONS OF A/D CONVERTER The A/D converter of the 78K/0 series is a successive approximation type with an 8-bit resolution and eight channels. Although only a select mode is supported as the operation mode, conversion can be started by an external trigger. If the external trigger is not used, the analog data of a selected channel is repeatedly converted into a digital signal. The A/D converter is set by the A/D converter mode register (ADM), A/D converter input select register (ADIS), external interrupt mode register 1 (INTM1), and A/D current cut select register (IEAD). Caution IEAD is provided only to the PD78098 and 78098B subseries. 299 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-1. Format of A/D Converter Mode Register (PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 78083, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries, PD78070A, 78070AY) Symbol ADM 7 CS 6 TRG 5 FR1 4 FR0 3 2 1 0 HSC Address FF80H At reset 01H R/W R/W ADM3 ADM2 ADM1 ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Selects analog input channel FR1 FR0 HSC Selects A/D conversion timeNote 1 At fX = 5.0 MHz MCS = 1 MCS = 0 At fX = 4.19 MHz MCS = 1 80/fX (19.1 s) MCS = 0 160/fX (38.1 s) 0 0 1 1 Others 0 1 0 0 1 1 0 1 80/fX (setting prohibited)Note 2 160/fX (32.0 s) 40/fX (setting prohibited)Note 2 80/fX (setting prohibited)Note 2 40/fX (setting prohibited)Note 2 80/fX (19.1 50/fX (setting prohibited)Note 2 100/fX (20.0 s) s) s) 50/fX (setting prohibited)Note 2 100/fX (23.8 100/fX (20.0 s) Setting prohibited 200/fx (40.0 s) 100/fX (23.8 s) 200/fX (47.7 s) TRG 0 1 No external trigger (software start) Selects external trigger Conversion started by external trigger (hardware start) CS 0 1 Stops operation Starts operation Controls A/D conversion operation Notes 1. Set the A/D conversion time to 19.1 s or longer. 2. These settings are prohibited because the A/D conversion time is less than 19.1 s. Cautions 1. To reduce the power consumption of the A/D converter when the standby function is used, stop the A/D conversion operation by clearing bit 7 (CS) to 0, and then execute the HALT or STOP instruction. 2. To resume the A/D conversion operation which has been once stopped, clear the interrupt request flag (ADIF) to 0 and then start the A/D conversion operation. Remarks 1. fX : main system clock oscillation frequency 2. MCS : bit 0 of the oscillation mode select register (OSMS) 300 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-2. Format of A/D Converter Mode Register (PD78098, 78098B subseries) Symbol ADM 7 CS 6 TRG 5 FR1 4 FR0 3 2 1 0 HSC Address FF80H At reset 01H R/W R/W ADM3 ADM2 ADM1 ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Selects analog input channel FR1 0 0 1 1 Others FR0 0 1 0 0 HSC 1 1 0 1 80/fXX (20.0 s) Selects A/D conversion timeNote 1 40/fXX (setting prohibited)Note 2 50/fXX (setting prohibited)Note 2 100/fXX (25.0 s) Setting prohibited TRG 0 1 No external trigger (software start) Selects external trigger Conversion started by external trigger (hardware start) CS 0 1 Stops operation Starts operation Controls A/D conversion operation Notes 1. Set the A/D conversion time to 19.1 s or longer. 2. These settings are prohibited because the A/D conversion time is less than 19.1 s. Cautions 1. To reduce the power consumption of the A/D converter when the standby function is used, stop the A/D conversion operation by clearing bit 7 (CS) to 0, and then execute the HALT or STOP instruction. 2. To resume the A/D conversion operation which has been once stopped, clear the interrupt request flag (ADIF) to 0 and then start the A/D conversion operation. Remarks 1. fXX : main system clock frequency 2. ( ) : fXX = 4.0 MHz 301 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-3. Format of A/D Converter Mode Register (PD780018, 780018Y subseries) Symbol ADM 7 CS 6 TRG 5 FR1 4 FR0 3 2 1 0 HSC Address FF80H At reset 01H R/W R/W ADM3 ADM2 ADM1 ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Selects analog input channel FR1 FR0 HSC Selects A/D conversion timeNote 1 At fX = 5.0 MHz At fX = 4.19 MHz 80/fX (19.1 s) 40/fX (setting prohibited)Note 2 50/fX (setting prohibited)Note 2 0 0 1 1 Others 0 1 0 0 1 1 0 1 80/fX (setting prohibited)Note 2 40/fX (setting prohibited)Note 2 50/fX (setting prohibited)Note 2 100/fX (20.0 s) Setting prohibited TRG 0 1 No external trigger (software start) Selects external trigger Conversion started by external trigger (hardware start) CS 0 1 Stops operation Starts operation Controls A/D conversion operation Notes 1. Set the A/D conversion time to 19.1 s or longer. 2. These settings are prohibited because the A/D conversion time is less than 19.1 s. Cautions 1. To reduce the power consumption of the A/D converter when the standby function is used, stop the A/D conversion operation by clearing bit 7 (CS) to 0, and then execute the HALT or STOP instruction. 2. To resume the A/D conversion operation which has been once stopped, clear the interrupt request flag (ADIF) to 0 and then start the A/D conversion operation. Remark fX : main system clock oscillation frequency 302 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-4. Format of A/D Converter Input Select Register Symbol ADIS 7 0 6 0 5 0 4 0 3 2 1 0 Address FF84H At reset 00H R/W R/W ADIS3 ADIS2 ADIS1 ADIS0 ADIS3 ADIS2 ADIS1 ADIS0 0 0 0 0 0 0 0 0 1 Others 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Selects number of analog input channels No analog input channel (P10-P17) 1 channel (ANl0, P11-P17) 2 channels (ANl0, ANl1, P12-P17) 3 channels (ANl0-ANl2, P13-P17) 4 channels (ANl0-ANl3, P14-P17) 5 channels (ANl0-ANI4, P15-P17) 6 channels (ANl0-ANI5, P16-P17) 7 channels (ANI0-ANl6, P17) 8 channels (ANI0-ANI7) Setting prohibited Cautions 1. Set analog input channels in the following steps: <1> Set the number of analog input channels by using ADIS. <2> Select one channel whose data is to be converted, from the channels selected by ADIS, by using the A/D converter mode register (ADM). 2. The internal pull-up resistor is not used to the channel selected by ADIS as an analog input channel, regardless of the value of the bit 1 (PUO1) of the pull-up resistor option register L (PUOL). 303 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-5. Format of External Interrupt Mode Register 1 (PD78054, 78054Y, 78078, 78078Y, 78098, 780018, 780018Y, 78058F, 78058FY, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY) Symbol INTM1 7 ES71 6 ES70 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 Address FFEDH At reset 00H R/W R/W ES41 0 0 1 1 ES40 0 1 0 1 Selects valid edge of INTP3 Falling edge Rising edge Setting prohibited Both rising and falling edges ES51 0 0 1 1 ES50 0 1 0 1 Selects valid edge of INTP4 Falling edge Rising edge Setting prohibited Both rising and falling edges ES61 0 0 1 1 ES60 0 1 0 1 Selects valid edge of INTP5 Falling edge Rising edge Setting prohibited Both rising and falling edges ES71 0 0 1 1 ES70 0 1 0 1 Selects valid edge of INTP6 Falling edge Rising edge Setting prohibited Both rising and falling edges 304 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-6. Format of External Interrupt Mode Register 1 (PD78064, 78064Y, 780058, 780058Y, 780308, 780308Y, 78064B subseries) Symbol INTM1 7 0 6 0 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 Address FFEDH At reset 00H R/W R/W ES41 0 0 1 1 ES40 0 1 0 1 Selects valid edge of INTP3 Falling edge Rising edge Setting prohibited Both rising and falling edges ES51 0 0 1 1 ES50 0 1 0 1 Selects valid edge of INTP4 Falling edge Rising edge Setting prohibited Both rising and falling edges ES61 0 0 1 1 ES60 0 1 0 1 Selects valid edge of INTP5 Falling edge Rising edge Setting prohibited Both rising and falling edges 305 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-7. Format of External Interrupt Mode Register 1 (PD78083 subseries) Symbol INTM1 7 0 6 0 5 0 4 0 3 0 2 0 1 ES41 0 ES40 Address FFEDH At reset 00H R/W R/W ES41 0 0 1 1 ES40 0 1 0 1 Selects valid edge of INTP3 Falling edge Rising edge Setting prohibited Both rising and falling edges Caution Be sure to clear bits 2 through 7 to 0. Figure 9-8. Format of A/D Current Cut Select Register (PD78098, 78098B subseries) Symbol IEAD 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IEAD0 Address F8E2H At reset 00H R/W R/W IEAD0 0 1 Controls connection between AVDD and AVREF0 Disconnects AVDD from AVREF0 Connects AVDD and AVREF0 306 CHAPTER 9 APPLICATIONS OF A/D CONVERTER 9.1 Level Meter In this application example, the analog voltage input to the A/D converter is displayed on an LED matrix consisting of 4 x 4, i.e., 16 LEDs. Because a level meter has been included in this example, the LED display is given in decibel units. Figure 9-9 shows the circuit of the level meter, and Figure 9-10 shows the relations between the result of the A/D conversion and the number of display digits. Figure 9-9. Example of Level Meter Circuit PD78054 P60 P61 P62 P63 ANIn P64 P65 P66 P67 = Figure 9-10. A/D Conversion Result and Display LED(Units) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0AH 12H 20H 2EH 39H 40H 48H 51H 5BH 66H 72H 80H 90H A2H B5H FFH -22 -17 -12 -9 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 6 Display value [dB] Display level 307 CHAPTER 9 APPLICATIONS OF A/D CONVERTER The level meter in this example operates with specifications <1> through <3> below. <1> Measurement method A/D conversion is performed every 20 ms, and the average value of four previous data is calculated and displayed on the LEDs. <2> Display method The LED display is updated every 20 ms. The LED matrix consists of 4 x 4 = 16 LEDs and performs dynamic display. For the dynamic display, 8-bit timer/event counter 1 (interval time: 2 ms) is used. <3> Peak hold Holding the maximum display level for a specific period (1 second) is called peak hold. Even if the display level drops during a specific period, only the LED at the maximum display level is held. Therefore, the hold period of the hold level is 20 ms to 1 s. Figure 9-11. Concept of Peak Hold Specific period (1 second) Hold level Display level 6 6 6 5 6 4 6 5 7 7 8 8 9 9 9 8 9 7 9 6 9 5 9 5 4 4 4 3 4 3 5 5 6 6 6 2 (1) Description of package 308 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Name ADDAT DSPLEV HLDLEV CT20MS CT1S DIGCNT DSPDAT WORKCT Usage Stores A/D conversion value Stores display level Stores hold level Counter measuring 20 ms Counter measuring 1 s Display digit counter Stores display data Work counter for loop processing 4 1 Attribute SADDR Bytes 4 1 Name T20MSF T1SF Set every 20 ms Set every 1 s Usage * A/D converter * 8-bit timer/event counter 1 * P6 * OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit * ADM = #1000xxx1B ; Selects channel of A/D converter and starts operation * TCL1 = #10111011B ; Interval time of 2 ms of 8-bit timer/event counter 1 TMC1 = #00000001B CR10 = 130 * P6 output mode * Makes P6 output latch low * Enables INTTM1 interrupt 309 CHAPTER 9 APPLICATIONS OF A/D CONVERTER * A/D conversion processing Call LEVEL at least once every 20 ms from the main processing. The LEVEL processing performs A/D conversion processing only when 20 has elapsed. * LED display The 4 x 4 LED matrix performs dynamic display by using the interrupt processing of 8-bit timer/event counter 1 (interval: 2 ms). The interrupt processing of 8-bit timer/event counter 1 sets the T20MSF (loading of A/D conversion value) and T1SF (end of hold period) used for the A/D conversion processing at an interval of 2 ms. (2) Example of use EXTRN MOV MOV MOV CLR1 LEVEL,CT20MS,CT1S CT20MS,#10 CT1S,#50 TMC2,#00100110B TMMK3 ; Turns OFF LED display P6=#00H PM6=#00000000B OSMS=#00000001B ADM=#10000001B TCL1=#10111011B CR10=#130 TMC1=#00000001B CLR1 TMMK1 EI ; Does not use divider circuit ; ANI0 pin starts operation ; Sets 8-bit timer/event counter 1 to 2 ms ; Enables 8-bit timer/event counter 1 interrupt 310 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (3) SPD chart LEVEL IF: 20 ms elapses (T20MSF = 1) THEN Clears T20MSF Stores A/D conversion value to memory Averages four previous A/D conversion values (FOR: WORKCT = #0; WORKCT < #16; WORKCT + +) IF: conversion result > display level comparison data THEN Updates comparison data ELSE BREAK Stores display data to memory IF: less then 1 second (T1SF = 0) THEN IF: hold level < display level THEN Sets display level to hold level ELSE Clears T1SF Sets display level to hold level Converts display level and hold level to segment signal Stores digit signal and segment signal to memory in combination INTTM1 Selects register bank 0 Outputs OFF signal to digit and segment Outputs memory contents indicated by digit counter Increments digit counter Decrements 20 ms counter IF: 20 ms elapses (CT20MS = 0) THEN Sets 20 ms counter to 10 Sets 20 ms elapse status Sets T20MSF Decrements 1-s counter IF: 1 second elapses (CT1S = 0) THEN Sets 1-s counter to 50 Sets 1-s elapse status Sets T1SF 311 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (4) Program list PUBLIC AD_DAT ADDAT: DSPLEV: HLDLEV: CT20MS: CT1S: DIGCNT: DSPDAT: WORKCT: AD_FLG T20MSF T1SF VETM1 DSEG DS DS DS DS DS DS DS DS BSEG DBIT DBIT CSEG DW AT 24H INTTM1 LEVEL,HLDLEV,DSPLEV,CT20MS,CT1S SADDR 4 1 1 1 1 1 4 1 ; ; ; ; ; ; ; A/D conversion result storage area Display level value Hold level value 20 ms counter 1 s counter Display digit counter Display data ; Measures 20 ms ; Measures 1 s ; Sets vector address of 8-bit timer/event counter 1 AD_SEG CSEG ;********************************* * Sets level meter data ;********************************* LEVEL: IF_BIT(T20MSF) CLR1 T20MSF A=ADCR A<->ADDAT A<->ADDAT+1 A<->ADDAT+2 A<->ADDAT+3 ; Checks 20 ms ; Inputs A/D conversion value ; Stores A/D conversion value ; Averages four A/D conversion values AX=#0H ; Data storage address HL=#ADDAT for(WORKCT=#0;WORKCT<#4;WORKCT++) A+=[HL] HL++ ; Carry if_bit(CY) ; Higher digit X++ endif next A<->X C=#4 AX/=C if(C>=#2) (A) X++ endif ; ; ; ; Averages four values AX/C = AX (quotient) ... C (remainder) Remainder processing (2 or higher is carried) Carry processing HL=#LEVTBL ; Conversion result storage register B=#0 for(WORKCT=#0;WORKCT<#16;WORKCT++) ; Compares data if(X>=[HL+B]) (A) B++ else break endif next 312 CHAPTER 9 APPLICATIONS OF A/D CONVERTER DSPLEV=B (A) if_bit(!T1SF) X=HLDLEV (A) if(X ; Determines display data ; 1 s (hold level updated) ; Compares hold and display levels ; Creates display level ; Creates hold level ; Sets segment signal of first digit ; Sets digit signal ; Sets segment signal of second digit ; Sets digit signal ; Sets segment signal of third digit ; Sets digit signal ; Sets segment signal of fourth digit ; Sets digit signal 313 CHAPTER 9 APPLICATIONS OF A/D CONVERTER RET LEVTBL: DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DSPTBL: DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW HLDTBL: DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW $EJECT 0000000000000000B 0000000000000001B 0000000000000010B 0000000000000100B 0000000000001000B 0000000000010000B 0000000000100000B 0000000001000000B 0000000010000000B 0000000100000000B 0000001000000000B 0000010000000000B 0000100000000000B 0001000000000000B 0010000000000000B 0100000000000000B 1000000000000000B 0000000000000000B 0000000000000001B 0000000000000011B 0000000000000111B 0000000000001111B 0000000000011111B 0000000000111111B 0000000001111111B 0000000011111111B 0000000111111111B 0000001111111111B 0000011111111111B 0000111111111111B 0001111111111111B 0011111111111111B 0111111111111111B 1111111111111111B 0AH 12H 20H 2EH 39H 40H 48H 51H 5BH 66H 72H 80H 90H 0A2H 0B5H 0FFH 314 CHAPTER 9 APPLICATIONS OF A/D CONVERTER ;********************************* * Level meter data ;********************************* TM1_SEG CSEG INTTM1: SEL RB0 P6=#00000000B HL=#DSPDAT B=DIGCNT (A) P6=[HL+B] (A) DIGCNT++ DIGCNT&=#00000011B CT20MS-if(CT20MS==#0) CT20MS=#10 SET1 T20MSF CT1S-if(CT1S==#0) CT1S=#50 SET1 T1SF endif endif RETI ; Turns OFF digit and segment signals ; 20 ms? ; Sets initial counter value ; 1s? ; Sets initial counter value 315 CHAPTER 9 APPLICATIONS OF A/D CONVERTER 9.2 Thermometer In this application example, a temperature in a range of -20C to +50C is measured by using a thermistor (6 k/ 0C) as a temperature sensor. Changes in the resistance of the thermistor with respect to temperature are given by the following expression: R = R0exp { B (1/T - 1/T0) } where, R : resistance at given temperature T [K] T : given temperature [K] R0 : resistance at reference temperature T0 [K] T0 : reference temperature [K] B : constant obtained by reference temperature T0 [K] and T0 [K] Constant B changes with the temperature. This constant can be calculated by changing the above expression as follows: B= 1 R In R0 (1/T-1/T0) Figure 9-12 shows a circuit example. This circuit is designed to input 0 V at -20C, and 5 V at + 50C. Figure 9-12. Circuit Example of Thermometer Th PD78054 + - ANIn 316 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Because the characteristic of the thermistor is non linear in this example, the input analog voltage is not converted to a temperature in a range of -20 C to +50 C through calculation but by comparison with table data. This conversion result is stored to RAM (DSPDAT) as 2-digit BCD. Figure 9-13 shows the characteristics of the thermistor, and Table 9-1 shows the relations between temperature and A/D conversion value. To measure the temperature, four conversion values are averaged and converted to a temperature. The result of the conversion is stored in a display area. Therefore, the data is updated once every four times. For example, if measurement processing is executed every 250 ms, the display updating cycle is 1 second. Figure 9-13. Temperature vs. Output Characteristic (%) 100 90 Percentage of output characteristic 80 70 60 50 40 30 20 10 0 -20 -10 0 10 20 Temperature 30 40 50 (C) 317 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Table 9-1. A/D Conversion Value and Temperature Conversion Value 00 01 04 07 0A 0C 0F 12 16 19 1C 1F 23 26 2A 2D 31 35 Temperature [C] -20.0 -19.5 -18.5 -17.5 -16.5 -15.5 -14.5 -13.5 -12.5 -11.5 -10.5 -9.5 -8.5 -7.5 -6.5 -5.5 -4.5 -3.5 Conversion Value 38 3C 40 44 48 4C 50 54 58 5C 60 64 69 6D 71 75 7A 7E Temperature [C] -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 Conversion Value 82 86 8B 8F 93 97 9B 9F A3 A8 AC B0 B4 B7 BB BF C3 C7 Temperature [C] 15.5 16.5 17.5 18.5 19.5 20.5 21.5 22.5 23.5 24.5 25.5 26.5 27.5 28.5 29.5 30.5 31.5 32.5 Conversion Value CB CE D2 D6 D9 DC E0 E3 E7 EA ED F0 F3 F6 F9 FC FE FF Temperature [C] 33.5 34.5 35.5 36.5 37.5 38.5 39.5 40.5 41.5 42.5 43.5 44.5 45.5 46.5 47.5 48.5 49.5 50.0 (1) Description of package T250MSF : 250-ms setting flag 318 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Name ADDAT DSPDAT CNTPRO WORKCT Usage Stores A/D conversion value Stores display data Test counter for number of inputs Work counter for loop processing Attribute SADDR Bytes 4 2 1 Name T250MSF MINUSF Usage Executes measurement processing when set Set when temperature is below zero 319 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (2) Example of use EXTRN EXTBIT AD_DAT DSEG CT250MS:DS LEDD: DS DIGCT: DS VETM3 CSEG DW THMETER,DSPDAT,CNTPRO MINUSF,T250MSF SADDR 1 4 1 AT 1EH INTTM3 ; 250 ms counter ; LED display area ; LED display digit counter ; Sets vector address of watch timer ; Sets watch timer to 1.95 ms MOV TMC2,#00100110B CLR1 TMMK3 . . . . CT250MS=#128 CNTPR0=#4 ADM=#10000011B . . . . ; Selects ANI1 pin and starts operation ;********************************************** ; Watch timer interrupt processing ; Interval time: 1.95 ms ;********************************************** INTTM3: ; 1.95 ms interrupt processing . . . . DBNZ CT250MS,$RTNTM3 ; 250 ms elapses MOV CT250MS,#128 SET1 T250MSF RTNTM3: . . . . RETI 320 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (3) SPD chart THMETER IF: 250 ms elapses (T250MS = 1) THEN Clears T250MS Stores A/D conversion value to memory IF: four values stored in memory THEN Averages four A/D conversion values (FOR: WORKCT = #0; WORKCT < #70; WORKCT + +) IF: conversion result > comparison data for temperature conversion THEN Updates comparison data ELSE BREAK IF: minus temperature data THEN Sets minus status Sets MINUSF Converts temperature data to decimal number and stores in memory 321 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (4) Program list PUBLIC AD_DAT ADDAT: DSPDAT: CNTPR0: WORKCT: DSEG DS DS DS DS THMETER,DSPDAT,CNTPR0,T250MSF,MINUSF SADDR 4 2 1 1 ; A/D conversion result storage area ; Display data ; Tests number of inputs AD_FLG BSEG T250MSF DBIT MINUSF DBIT TH_SEG CSEG ;********************************* * Sets temperature data ;********************************* THMETER: if_bit(T250MSF) CLR1 T250MSF A=ADCR A<->ADDAT A<->ADDAT+1 A<->ADDAT+2 A<->ADDAT+3 ; Sets 250 ms ; Sets minus data ; 250 ms CNTPR0-if(CNTPR0==#0) CNTPR0=#4 AX=#0H HL=#ADDAT ; Data storage address for(WORKCT=#0;WORKCT<#4;WORKCT++) A+=[HL] HL++ if_bit(CY) ; Carry occurs X++ ; Carry endif next A<->X C=#4 AX/=C if(C>=#2) (A) X++ endif ; AX/C = AX (quotient) ... C (remainder) ; Remainder processing (2 digits or more carried) ; Carry processing A=X ; Converts to temperature data B=#0 HL=#THRTBL if(A==#0FFH) B=#70 else for(WORKCT=#0;WORKCT<#70;WORKCT++) if(X>=[HL+B]) (A) B++ else break endif next 322 CHAPTER 9 APPLICATIONS OF A/D CONVERTER endif CLR1 MINUSF A=#20 B-=A if_bit(CY) SET1 MINUSF A=#0 A-=B A<->B endif X=#0 A=B A<->X C=#10 AX/=C DSPDAT=C (A) (DSPDAT+1)=X (A) endif endif RET ; Temperature data 20 ; To decimal conversion ; Absolute value of data ; Decimal conversion ; Temperature data/10 ; Updates display data 323 CHAPTER 9 APPLICATIONS OF A/D CONVERTER THRTBL; ; DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1 4 7 0AH 0CH 0FH 12H 16H 19H 1CH 1FH 23H 26H 2AH 2DH 31H 35H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 69H 6DH 71H 75H 7AH 7EH 82H 86H 8BH 8FH 93H 97H 9BH 9FH 0A3H 0A8H 0ACH 0B0H 0B4H 0B7H 0BBH 0BFH 0C3H 0C7H 0CBH 0CEH 0D2H 0D6H ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; -19.5 -18.5 -17.5 -16.5 -15.5 -14.5 -13.5 -12.5 -11.5 -10.5 -9.5 -8.5 -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 +0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 17.5 18.5 19.5 20.5 21.5 22.5 23.5 24.5 25.5 26.5 27.5 28.5 29.5 30.5 31.5 32.5 33.5 34.5 35.5 36.5 324 CHAPTER 9 APPLICATIONS OF A/D CONVERTER DB DB DB DB DB DB DB DB DB DB DB DB DB 0D9H 0DCH 0E0H 0E3H 0E7H 0EAH 0EDH 0F0H 0F3H 0F6H 0F9H 0FCH 0FFH ; ; ; ; ; ; ; ; ; ; ; ; ; 37.5 38.5 39.5 40.5 41.5 42.5 43.5 44.5 45.5 46.5 47.5 48.5 49.5 325 CHAPTER 9 APPLICATIONS OF A/D CONVERTER 9.3 Analog Key Input In this example, sixteen keys are input by using the A/D converter. To input keys, a circuit must be designed so that a voltage peculiar to a key is input to the A/D converter when the key is pressed. Because sixteen keys are input in this example, VDD is divided by 16 and the voltage of each key is converted into a key code. Table 9-2 shows the relations between the input voltages and key codes (00H through 0FH). When no key input is made, the key code is 10H. Table 9-2. Input Voltage and Key Code Input Voltage V GND 1/16VDD 2/16VDD 3/16VDD 4/16VDD 5/16VDD 6/16VDD 7/16VDD 8/16VDD 9/16VDD 10/16VDD 11/16VDD 12/16VDD 13/16VDD 14/16VDD 15/16VDD VDD A/D Conversion Value 00-07H 08-17H 18-27H 28-37H 38-47H 48-57H 58-67H 68-77H 78-87H 88-97H 98-A7H A8-B7H B8-C7H C8-D7H D8-E7H E8-F7H F8-FFH Key Code 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H Figure 9-14 shows an example of the circuit that satisfies the above relations between the input voltages and key codes. Note, however, that this circuit gives a priority to the key with the lower number if two or more keys are pressed at the same time. 326 CHAPTER 9 APPLICATIONS OF A/D CONVERTER Figure 9-14. Example of Analog Key Input Circuit VDD R0 ANIn K1 R1 K0 K2 R2 PD78054 K14 R14 R15 K15 Resistances R0 through R15 used in the circuit in Figure 9-14 can be calculated by the following expression: n RK = K=1 n x R0 16-n Table 9-3 shows the resistances of R1 through R15 where R0 is 1 k in the above expression (the calculation result of a resistance may slightly different from the resistance of commercial resistors indicated by a color code). Table 9-3. Resistances of R1 through R5 Resistor No. R1 R2 R3 R4 R5 Resistance Value Resistor No. Resistance Value Resistor No. Resistance Value 68 75 82 100 120 R6 R7 R8 R9 R10 150 180 220 270 390 R11 R12 R13 R14 R15 560 750 1.3 k 2.7 k 8.2 k This program converts an input analog voltage into the corresponding key code shown in Table 9-2, absorbs chattering, and then stores the input voltage to RAM. To absorb chattering, a key code is assumed to be valid when it coincides with a given value five times in succession. For example, if an analog voltage is sampled every 5 ms, chattering of 20 to 25 ms is absorbed. If a key input is changed, a key change flag (KEYCHG) is set. 327 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (1) Description of package CHTENDF : Flag to test end of chattering absorption Name PASTDAT KEYDAT CHATCNT Usage Stores key code for chattering absorption Stores key code Chattering counter Attribute SADDR Bytes 1 Name KEYCHG CHTENDF Usage Set when key is changed Sets when chattering absorption ends * Call AKEYIN at fixed interval. * Input a key code after testing the key change flag. Note that this flag is not cleared by the subroutine and must be cleared after the flag has been tested. 328 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (2) Example of use EXTRN EXTRN EXTBIT VETM3 CSEG DW AKEYIN,KEYDAT,PASTDT,CHATCT KEYOFF KEYCHG,CHTENDF AT 1EH INTTM3 SADDR 1 ; Sets vector address of watch timer MAINDAT DSEG CT5MS: DS TMC2=#00100110B CLR1 TMMK3 CT5MS=#3 ; Sets OFF data as key data KEYDAT=#KEYOFF PASTDT=#KEYOFF ; Sets number of times of chattering to five CHATCT=#CHAVAL CLR1 CHTENDF CLR1 KEYCHG ; Selects ANI2 pin and starts operation ADM=#10000101B EI . . . . ; Key changed? if_bit(KEYCHG) CLR1 KEYCHG ; Key input processing endif . . . . ;********************************************** ; Watch timer interrupt processing ; Interval: 1.95 ms ;********************************************** ; 1.95 ms interrupt processing INTTM3: . . . . DBNZ CT5MS,$RTNTM3 ; 1.95 ms x 3 elapses MOV CT5MS,#3 CALL !AKEYIN RTNTM3: . . . . RETI 329 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (3) SPD chart AKEYIN Inputs and adjusts A/D conversion value (adds 8) IF: overflow occurs THEN Sets no key input status ELSE Decodes key IF: key input not changed THEN IF: chattering being absorbed THEN IF: chattering absorption ends THEN Sets chattering absorption status Sets CHTENDF IF: valid key changed THEN Updates key code Sets key change status ELSE Sets KEYCHG Updates comparison key code Sets chattering absorption start status Clears CHTENDF 330 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (4) Program list PUBLIC PUBLIC PUBLIC AK_DAT DSEG KEYDAT: DS PASTDT: DS CHATCT: DS AK_FLG BSEG KEYCHG DBIT CHTENDF DBIT KEYOFF CHAVAL EQU EQU 10H 5 AKEYIN,KEYDAT,PASTDT CHATCT,KEYOFF KEYCHG,CHTENDF SADDR 1 1 1 ; Key data storage area ; Chattering key data ; Chattering counter ; Key changed ; Chattering absorption end status ; OFF key data ; Number of times of chattering absorption AK_SEG CSEG ;****************************** * Analog key input ;****************************** AKEYIN: A=ADCR A+=#8 if_bit(CY) A=#KEYOFF else A>>=1 A>>=1 A>>=1 A>>=1 A&=0FH endif if(A==PASTDT) if_bit(!CHTENDF) CHATCT-if(CHATCT==#0) SET1 CHTENDF A=PASTDT if(A!=KEYDAT) KEYDAT=A SET1 KEYCHG endif endif endif endif PASTDT=A CHATCT=#CHAVAL-1 CLR1 CHTENDF endif RET ; Inputs A/D conversion value ; Corrects data ; Sets no key input status ; Decodes key ; No key change ; Chattering being absorbed ; End of chattering absorption ; Sets chattering absorption status ; Valid key changed ; Updates key data ; Sets key change status ; Updates previous key data ; Starts chattering absorption 331 CHAPTER 9 APPLICATIONS OF A/D CONVERTER 9.4 4-Channel Input A/D Conversion This section describes the method to scan four channels for A/D conversion. The A/D conversion operation is started by the software. The analog voltages input to the selected four channels are converted into digital signals. The result of the A/D conversion of each channel is stored in RAM. An interrupt request is generated by using 8-bit timer/event counter 1. The result of the conversion is loaded and channel is converted in the processing of this interrupt request. Because 8-bit timer/event counter 1 is set to 10 ms, it is not necessary to measure the wait time of the A/D conversion. Caution To change the interrupt time, make the following setting: * Set timer longer than A/D conversion end time + Interrupt entry return time + Interrupt processing time. * Test flags that indicate the end of the conversion. Figure 9-15. Timing Chart in 4-Channel Scan Mode INTTM2 10 ms ADCR ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 ANI2 ANI3 ANI0 ADIn 0 1 2 3 0 1 2 3 0 1 332 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (1) Description of package * Output parameter M_CH0 : Stores conversion result of channel 0 M_CH1 : Stores conversion result of channel 1 M_CH2 : Stores conversion result of channel 2 M_CH3 : Stores conversion result of channel 3 Name M_CH0 M_CH1 M_CH2 M_CH3 M_MODE Usage Channel 0 conversion result storage area Channel 1 conversion result storage area Channel 2 conversion result storage area Channel 3 conversion result storage area Mode storage area Attribute SADDR SADDR SADDR SADDR SADDR Bytes 1 1 1 1 1 * A/D converter * 8-bit timer/event counter 1 * Port 1 (P10-P13) * * * * OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit ADM = #1000xxxxB ADIS = #00000100B TCL1 = #00001110B TMC1 = #00000001B CR10 = #81 ; Selects A/D converter channel and starts operation ; Selects number of A/D converter channels ; Interval time of 8-bit timer/event counter 1: 10 ms * Enables TMMK1 interrupt 333 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (2) Example of use EXTRN M_CH0,M_CH1,M_CH2,M_CH3,M_MODE ;****************************************** ; Initialize ;****************************************** M4 CSEG ; RES_STA: SEL RB0 ; DI ; . . . . ; Does not use divider circuit OSMS=#00000001B ; Starts A/D operation and selects external trigger channel 0 ADM=#10000001B ; Selects analog input channel 4 ADIS=#00000100B ; Sets modulo register 81 CR10=#81 ; Count clock: 8.2 kHz TCL1=#00001110B ; Enables 8-bit timer/register 1 operation TMC1=#00000001B ; Clears timer 1 interrupt request flag CLR1 TMIF1 ; Enables timer 1 interrupt CLR1 TMMK1 ; EI ; Sets initial value (0 channel) to mode area M_MODE=#0 . . while(forever) . . A=M_CH0 . . A=M_CH1 . . A=M_CH2 . . A=M_CH3 . . ; ; A data of channel 0 ; A data of channel 1 ; A data of channel 2 ; A data of channel 3 (3) SPD chart [A/D conversion processing] KASAN Loads conversion result of channel for previous A/D conversion Changes channel ADM selects changed channel 334 CHAPTER 9 APPLICATIONS OF A/D CONVERTER (4) Program list ;******************************************** ; A/D conversion ;******************************************** ; $PC(054) ; ; PUBLIC M_CH0,M_CH1,M_CH2,M_CH3,M_MODE ; ; VEINTM1 CSEG AT 24H DW KASAN ;******************************************** ; RAM definition ;******************************************** DSEG SADDR ; M_CH0: DS 1 ; M_CH1: DS 1 ; M_CH2: DS 1 ; M_CH3: DS 1 ; M_MODE: DS 1 ; ; CSEG KASAN: ; SEL RB2 ; switch(M_MODE) ; case 0: ; M_CH0=ADCR (A) ; M_MODE++ ; ADM=#10000011B ; break ; case 1: ; M_CH1=ADCR (A) ; M_MODE++ ; ADM=#10000101B ; break ; case 2: ; M_CH2=ADCR (A) ; M_MODE++ ; ADM=#10000111B ; break ; case 3: ; M_CH3=ADCR (A) ; M_MODE=#0 ; ADM=#10000001B ; break ; ends ; RETI END Area for channel 0 addition Area for channel 1 addition Area for channel 2 addition Area for channel 3 addition Mode storage area Selects bank 2 Channel currently selected? Channel 0: Transfers conversion result to RAM Select channel 1: Channel 1: Transfers conversion result to RAM Selects channel 2 Channel 2: Transfers conversion result to RAM Selects channel 3 Channel 3: Transfers conversion result to RAM Selects channel 0 335 [MEMO] 336 CHAPTER 10 APPLICATIONS OF D/A CONVERTER The D/A converter of the 78K/0 series consists of two voltage output type D/A converter channels with an 8-bit resolution. This D/A can be used in two modes: normal mode and real-time output mode. In the normal mode, the output trigger is writing data to the D/A conversion value setting registers 0 and 1 (DACS0 and 1). In the real-time output mode, the output is triggered by the interrupt requests (INTTM1 and 2) of 8-bit timer/event counters 1 and 2. In this mode, set data to DACS0 and DACS1 after an output trigger has been generated until the next output trigger is generated. The D/A converter is set by the D/A converter mode register. Figure 10-1. Format of D/A Converter Mode Register Symbol DAM 7 0 6 0 5 4 3 0 2 0 1 0 Address FF98H At reset 00H R/W R/W DAM5 DAM4 DACE1 DACE0 DACE0 Controls D/A converter channel 0 0 1 Stops D/A conversion operation Enables D/A conversion operation DACE1 Controls D/A converter channel 1 0 1 Stops D/A conversion operation Enables D/A conversion operation DAM4 0 1 Operation mode of D/A converter channel 0 Normal mode Real-time output mode DAM5 0 1 Operation mode of D/A converter channel 1 Normal mode Real-time output mode Cautions 1. To use the D/A converter, set the multiplexed port pins in the input mode and disconnect the pull-up resistor. 2. Be sure to clear bits 2, 3, 6, and 7 to 0. 3. The output goes into a high-impedance state when D/A conversion operation is stopped. 4. The output trigger in the real-time output mode is INTTM1 for channel 0 and INTTM2 for channel 1. 337 CHAPTER 10 APPLICATIONS OF A/D CONVERTER 10.1 SIN Wave Output This section introduces an example that outputs a SIN wave with a frequency of 50 Hz by using the real-time output mode of D/A converter channel 0. After the output operation has been started, an analog value resulting from the D/A conversion specified by the D/A conversion value setting register 0 (DACS0) is output, and the next output data is set to DACS0 by interrupt processing. The value set by the interrupt processing is output at the next timing of 8-bit timer/event counter 1. Figure 10-2 shows the output data writing timing and analog output timing. Figure 10-2. Analog Output and Output Data Storage Timing 8-bit timer interrupt request Writing output data D1 D2 D3 D4 D5 D6 D7 D8 Analog output D0 D1 D2 D3 D4 D5 D6 D7 The interval time of 8-bit timer/event counter 1 is set to about 668 s and a 50-Hz D/A output wave is generated as shown in Figure 10-3. The SIN wave output data is stored in ROM. Data are sequentially referenced by the interrupt processing of 8bit timer/event counter 1 and written to DACS0. Table 10-1 shows the voltages for SIN wave output and set values. Figure 10-3. D/A Output Waveform [V] 5 4 3 2 1 Voltage 0 24 48 72 96 120 144 168 192 216 Degree 240 264 288 312 336 360 [degree] 338 CHAPTER 10 APPLICATIONS OF A/D CONVERTER Table 10-1. Voltage of SIN Wave Output and Preset Value Degree 0 12 24 36 48 60 72 84 96 108 120 132 144 156 168 Voltage (V) 2.5000 3.0200 3.5168 3.9695 4.3579 4.6651 4.8776 4.9863 4.9863 4.8776 4.6651 4.3579 3.9695 3.5168 3.0200 Set Value 80H 9BH B4H CBH DFH EFH FAH FFH FFH FAH EFH DFH CBH B4H 9BH Degree 180 192 204 216 228 240 252 264 276 288 300 312 324 336 348 Voltage (V) 2.5000 1.9802 1.4832 1.0305 0.6421 0.3349 0.1224 0.0137 0.0137 0.1224 0.3349 0.6421 1.0305 1.4832 1.9802 Set Value 80H 65H 4CH 35H 21H 11H 06H 01H 01H 06H 11H 21H 35H 4CH 65H Remark The analog voltage output to the ANO0 pin is determined by the following expression: ANO0 pin output voltage = AVREF1 x DACS0 256 Caution The voltage values shown in Table 10-1 is rounded off at the fifth position after the decimal point. However, the preset value is calculated with the data before rounding off. The resultant data is rounded off at the first position after the decimal point. 339 CHAPTER 10 APPLICATIONS OF A/D CONVERTER The output analog value is processed by the SIN wave conversion circuit shown in Figure 10-4 to create a SIN wave without step. Figure 10-4. SIN Wave Conversion Circuit 0.012 F Amplifier 1 F 270 k ANO0 10 kW SlN wave Integrating circuit Lowpass filter (1) Description of package * Data definition reference name SDATA : First address of SIN wave output data to be stored to DACS0 register ENDDAT : Last pointer of SIN wave data * Input/output parameter C_DATA : ROM data counter Name C_DATA Usage Counter indicating pointer that extracts SIN wave output data Attribute SADDR Bytes 1 340 CHAPTER 10 APPLICATIONS OF A/D CONVERTER * D/A converter * 8-bit timer/event counter 1 * OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit * PM13 = #xxxxxxx1B ; Sets port 13 in input mode * TCL1 = #xxxx1001B ; Interval of 8-bit timer/event counter: 668 s TMC1 = #000000x0B CR10 = #174 * DACS0 = #80H DAM = #00000001B ; Sets D/A converter ; Sets D/A converter in real-time output mode ; Enables operation of 8-bit timer/event counter 1 and enables interrupt * SET1 DAM.4 * SET1 TCE1 CLR1 TMIF1 CLR1 TMMK1 Caution To prevent output of a value on resetting and starting, once set the normal mode and write the initial value to the D/A conversion value setting register 0 (DACS0), and then output the initial value. After that, set the real-time output mode, and enable the operation of 8-bit timer/event counter 1 and interrupt. If D/A conversion is started in the real-time output mode after reset and start with the initial value set to the DACS0 register, 0 V (data D0 in Figure 10-2. Analog Output and Output Data Storage Timing) is output. 341 CHAPTER 10 APPLICATIONS OF A/D CONVERTER (2) Example of use EXTRN C_DATA,SDATA,ENDDAT ; ; Real-time output port setting flag F_RIARU EQU DAM.4 ; . . ; Does not use divider circuit OSMS=#00000001B ; SIN_DAT; 8-bit timer 1. Count clock: 262 kHz TCL1=#00001001B ; 8-bit timer 1. Interval: 668 s CR10=#175-1 ; Disables 8-bit timer 1 operation TMC1=#00000000B ; ; ; HL=#SDATA ; B=C_DATA (A) ; DACS0=[HL+B] (A) ; Enables D/A conversion operation of channel 0 in normal mode DAM=#00000001B ; Sets P130 in input port mode PM13=#11111111B EI . . . . if_bit(SIN wave output data start) ; ; Sets channel 0 in real-time output mode SET1 F_RIARU ; Sets initial value to conversion value setting register C_DATA=#0 ; HL=#SDATA ; B=C_DATA (A) ; DACS0=[HL+B] (A) ; Enables 8-bit timer 1 operation SET1 TCE1 ; Clears 8-bit timer 1 request flag CLR1 TMIF1 ; Enables 8-bit timer 1 interrupt CLR1 TMMK1 ; Enables D/A operation SET1 DACE0 ; endif . . . . (3) SPD chart INTTM1 Switches register bank 3 Increments ROM counter Table reference of SIN wave output data to be stored next to DACS0 register and writes it to DACS0 (if: ROM counter last pointer) THEN Writes initial value 0FFH to ROM counter 342 CHAPTER 10 APPLICATIONS OF A/D CONVERTER (4) Program list PUBLIC ; VETIM1 C_DATA,SDATA,ENDDAT CSEG DW AT 24H INTTM1 ENDDAT EQU 1DH ; SIN wave data 1 cycle end value ; SINRAM DSEG SADDR C_DATA: DS 1 ; ROM data counter ;******************************************************** ; SIN wave data change interrupt processing ;******************************************************** SINDAT CSEG INTTM1: SEL RB3 ; Sets bank 3 C_DATA++ ; Increments ROM data counter B=C_DATA (A) ; Refers to SIN wave output data HL=#SDATA ; DACS0=[HL+B] (A) ; Stores data if(C_DATA >= #ENDDAT) ; End of 1 cycle of SIN wave? C_DATA=#0FFH ; Initializes ROM data counter endif ; RETI ; SDATA: ; DB 09BH ; SIN wave data DB 0B4H ; DB 0CBH ; DB 0DFH ; DB 0EFH ; DB 0FAH ; DB 0FFH ; DB 0FFH ; DB 0FAH ; DB 0EFH ; DB 0DFH ; DB 0CBH ; DB 0B4H ; DB 09BH ; DB 080H ; DB 065H ; DB 04CH ; DB 035H ; DB 021H ; DB 011H ; DB 006H ; DB 001H ; DB 001H ; DB 006H ; DB 011H ; DB 021H ; DB 035H ; DB 04CH ; DB 065H ; DB 080H ; END 343 [MEMO] 344 CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT This chapter describes the real-time output function of the 78K/0 series. The real-time output function is used to output data set in advance in the real-time output buffer registers (RTBL and RTBH) to an external device by transferring the data to an output latch by hardware as soon as a timer interrupt request or external interrupt request occurs. By using the real-time output port function, a jitter free signal can be output. Therefore, this function is ideal for controlling a stepping motor. The real-time output port can be set in the port mode or real-time output mode in 1bit units. The real-time output data is written to the real-time output buffer registers (RTBL and RTBH). RTBL and RTBH are mapped to independent addresses in the SFR area. When an operation mode of 4 bits x 2 channels is selected, RTBL and RTBH can independently set data. When an operation mode of 8 bits x 1 channel is specified, data can be set to RTBL or RTBH by writing 8-bit data to either of RTBL or RTBH. The real-time output port is set by using the real-time output port mode register (RTPM), real-time output control register (RTPC), and port mode register 12 (PM12). 345 CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT Figure 11-1. Format of Real-Time Output Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address FF34H At reset 00H R/W R/W RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0 RTPMn Selects real-time output port (n = 0-7) 0 1 Port mode Real-time output port mode Cautions 1. When the real-time output port mode is used, the port that performs real-time output must be set in the output mode (by clearing the corresponding bits of the port mode register 12 (PM12) to 0). 2. Data cannot be set to the output latch of the port set in the real-time output port mode. To set an initial value, therefore, set data to the output latch before setting the real-time output port mode. Figure 11-2. Format of Real-Time Output Port Control Register Symbol RTPC 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF36H At reset 00H R/W R/W BYTE EXTR EXTR 0 1 Controls real-time output by INTP2 Does not use INTP2 as real-time output trigger Uses INTP2 as real-time output trigger BYTE 0 1 Operation mode of real-time output port 4 bits x 2 channels 8 bits x 1 channel The relationship between operation mode and output trigger of the real-time output port is shown in Table 11-1. Table 11-1. Operation Mode and Output Trigger of Real-Time Output Port BYTE 0 EXTR 0 1 1 0 1 8 bits x 1 channel Output Mode 4 bits x 2 channels RTBH Port Output INTTM2 INTTM1 INTTM1 INTP2 RTBL Port Output INTTM1 INTP2 346 CHAPTER 11 APPLICATIONS OF REAL-TIME OUTPUT PORT Figure 11-3. Format of Port Mode Register 12 Symbol 7 6 5 4 3 2 1 0 Address FF2CH At reset FFH R/W R/W PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120 PM12n Selects input/output mode of P12n pin (n = 0-7) 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) 347 CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT 11.1 Stepping Motor A 4-phase stepping motor is connected to the real-time output port (P120 through P123) and is controlled with 1-phase excitation pattern. A motor that rotates 1.8 degree per step is used for 1-phase excitation and is driven 200 revolutions per minute. The time required for 1 step is calculated by the following expression: 1 step = 60 seconds 200 revolutions x 360 degrees 1.8 degree Step = 1.5 ms The compare register (CR01) of 8-bit timer/event counter 1 is set to 1.5 ms and the real-time output buffer register (RTBL) is set. By using the real-time output port control register (RTPC), set the 4 bit x 2 channel real-time output mode, and the coincidence interrupt (INTTM1) of the 8-bit timer/event counter 1 as the output trigger (refer to Table 11-1). Figure 11-4 shows the phase excitation output pattern and output timing. Figure 11-4. Phase Excitation Output Pattern and Output Timing 1.5 ms 1-phase excitation pattern Port P123 P122 P121 P120 P120 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 P123 P121 INTTM1 P122 348 CHAPTER 11 APPLICATIONS OF REAL-TIME OUTPUT PORT (1) Description of package * Real-time output port * 8-bit timer/event counter 1 * OSMS = #00000001B ; Oscillation mode select register: does not use divider circuit * P12 = #xxxx0000B ; Sets P120-P123 in output port mode PM12 = #xxxx0000B * TCL1 = #xxxx1010B ; Timer clock select register 1 (count clock: 131 kHz) * CR10 = #195 ; Compare register (set to 1.5 ms) * TMC1 = #000000x1B ; 8-bit timer mode control register 1 (enables operation of 8-bit timer/event counter 1) * RTPM = xxxx1111B ; Real-time output port mode register (lower 4 bits are used as real-time output port) * RTPC = #00000000B ; Real-time output port control register (selects 4 bit x 2 channel mode and INTTM1 as output trigger) * RTBL = #00000001B * CLR1 TMIF1 * CLR1 TMMK1 ; Initial setting of real-time output buffer register ; Clears 8-bit timer/event counter 1 interrupt request flag ; Enables 8-bit timer/event counter 1 Clear the interrupt request flag of 8-bit timer/event counter 1 and enable the interrupt when the operation is started. 349 CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT (2) Example of use . . . OSMS=#00000001B TCL1=#00001010B CR10=#196-1 P12=#00000000B . . PM12=#11110000B . RTPM=#00001111B RTPC=#00000000B RTBL=#00000001B TMC1=#00000001B CLR1 TMIF1 CLR1 TMMK1 EI . . . ; ; ; ; ; ; ; ; ; ; ; ; Does not use divider circuit MORTER_DAT: 8-bit timer 1. Count clock: 131 kHz Sets compare register to 1.5 ms Sets P120-P123 in output port mode Sets low-order 4 bits in output port mode Uses INTTM1 as output trigger Enables 8-bit timer 1 operation Clears 8-bit timer 1 interrupt request flag Enables 8-bit timer 1 interrupt (3) SPD chart INTTM1 Suitches register bank 3 A RTBL (loads data currently output) (if: A < #00001000B) THEN Shifts A register 1 bit to left ELSE A #00000001B (returns to initial value) RTBL A (4) Program list CSEG AT 24H DW INTTM1 ;************************************************** ; Stepping motor data output processing ;************************************************** MOTER CSEG INTTM1: SEL RB3 A=RTBL if(A < #8) A <<= 1 else A=#01H endif RTBL=A RETI END VETIM1 ; Bank 3 ; ; Prepares next output data ; ; ; ; ; RTPL output data ; 350 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER The LCD controller/driver of the PD78064, 78064Y, 780308, 780308Y, and 78064B subseries is set by using the LCD display mode register (LCDM) and LCD display control register (LCDC). 351 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-1. Format of LCD Display Mode Register (PD78064, 78064Y, 78064B subseries) Symbol 7 6 5 4 3 0 2 1 0 Address FFB0H At reset 00H Bias R/W R/W LCDM LCDON LCDM6 LCDM5 LCDM4 LCDM2 LCDM1 LCDM0 0 0 0 0 1 Others 0 0 1 1 0 0 1 0 1 0 4 3 2 3 Static LCDM2 LCDM1 LCDM0 Time division 1/3 1/3 1/2 1/2 Setting prohibited LCDM6 LCDM5 LCDM4 At fXX = 5.0 MHz 0 0 0 0 Others 0 0 1 1 0 1 0 1 fW/29 fW/28 fW/27 fW/26 (76 Hz) (153 Hz) (305 Hz) (610 Hz) Selects LCD clockNote At fXX = 4.19 MHz fW/29 fW/28 fW/27 fW/26 (64 Hz) (128 Hz) (256 Hz) (512 Hz) At fXT = 32.768 kHz fW/29 fW/28 fW/27 fW/26 (64 Hz) (128 Hz) (256 Hz) (512 Hz) Setting prohibited LCDON 0 1 Enables/disables LCD display Display off (all segment outputs are unselect signal outputs) Display on Note The LCD clock is supplied by the watch timer. To perform LCD display, set the bit 1 (TMC21) of watch timer mode control register (TMC2) to 1. If TMC21 is reset to 0 during LCD display, supply of the LCD clock is stopped and the display is disturbed. Remarks 1. fW : watch timer clock frequency (fXX/27 or fXT) 2. fXX : main system clock frequency (fX or fX/2) 3. fX : main system clock oscillation frequency 4. fXT : subsystem clock oscillation frequency 352 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-2. Format of LCD Display Mode Register (PD780308, 780308Y subseries) Symbol 7 6 5 4 3 2 1 0 Address FFB0H At reset 00H R/W R/W LCDM LCDON LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0 LCDM2 LCDM1 LCDM0 0 0 0 0 1 Others 0 0 1 1 0 0 1 0 1 0 4 3 2 3 Static Time division 1/3 1/3 1/2 1/2 Bias Setting prohibited Note 1 LCDM3 Operation mode of LCD controller/driver Normal operation Supply voltage of LCD controller/driver Static display mode 2.0 to 5.5 V 1/3 bias mode 2.5 to 5.5 V 1/2 bias mode 2.7 to 5.5 V 0 1 Low-voltage operation 2.0 to 3.4 V LCDM6 LCDM5 LCDM4 At fXX = 5.0 MHz 0 0 0 0 Others 0 0 1 1 0 1 0 1 fW/29 (76 Hz) fW/28 (153 Hz) fW/27 (305 Hz) fW/26 (610 Hz) Setting prohibited Selects LCD clockNote At fXX = 4.19 MHz fW/29 (64 Hz) fW/28 (128 Hz) fW/27 (256 Hz) fW/26 (512 Hz) At fXT = 32.768 kHz fW/29 (64 Hz) fW/28 (128 Hz) fW/27 (256 Hz) fW/26 (512 Hz) LDON 0 1 Enables/disables LCD display Display off (all segment outputs are unselect signal outputs) Display on Notes 1. To lower the power consumption, clear LCDM3 to 0 when LCD display is not used. To manipulate LCDM3, be sure to turn off the LCD display. If TMC21 is cleared to 0 during LCD display, the supply of the LCD clock is stopped and the display is disturbed. 2. The LCD clock is supplied by the watch timer. To perform LCD display, set the bit 1 (TMC21) of watch timer mode control register (TMC2) to 1. If TMC21 is reset to 0 during LCD display, supply of the LCD clock is stopped and the display is disturbed. Remarks 1. fW : watch timer clock frequency (fXX/27 or fXT) 2. fXX : main system clock frequency (fX or fX/2) 3. fX : main system clock oscillation frequency 4. fXT : subsystem clock oscillation frequency 353 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-3. Format of LCD Display Control Register Symbol 7 6 5 4 3 0 2 0 1 LEPS 0 LIPS Address FFB2H At reset 00H R/W R/W LCDC LCDC7 LCDC6 LCDC5 LCDC4 LEPS 0 0 1 1 LIPS 0 1 0 1 Selects LCD drive power supply Does not supply power for LCD driving Supplies LCD driving power from VDD Supplies driving power from BIAS pin (BIAS and VLC0 pins are internally short-circuited) Setting prohibited LCDC7 LCDC6 LCDC5 LCDC4 Function of P80/S39-P97/ S24 pins Port pin 0 0 0 0 0 0 0 0 1 Others 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 P80-P97 P80-P95 P80-P93 P80-P91 P80-P87 P80-P85 P80-P83 P80, P81 None Segment pin None S24, S25 S24-S27 S24-S29 S24-S31 S24-S33 S24-S35 S24-S37 S24-S39 Setting prohibited Cautions 1. Pins that output segments cannot be used as output port pins even if 0 is set to the corresponding port mode register. 2. When pins that output segments are read as port pins, 0 is returned. 3. Pins set by LCDC to output segments are not used with the internal pull-up resistor, regardless of the values of the bits 0 and 1 (PUO8 and PUO9) of the pull-up resistor option register H (PUOH). 354 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER The LCD controller/driver of the PD78064, 78064Y, 780308, and 780308Y subseries is described next. (a) Function of LCD controller/driver The LCD controller/driver has the following functions: <1> Automatically outputs segment and common signals by automatically reading the display data memory. <2> Five types of display modes are available: * * * * * Static mode 1/2 duty mode (1/2 bias) 1/3 duty mode (1/2 bias) 1/3 duty mode (1/3 bias) 1/4 duty mode (1/3 bias) <3> Four types of frame frequencies can be selected in each display mode. <4> Up to 40 segment signal outputs (S0 through S39) and four common signal outputs (COM0 through COM3) are available. Sixteen segment outputs can be set in the input/output port mode in 2-bit units (P80/S39 through P87/S32, and P90/S31 through P97/S24). <5> Divider resistors for generating the LCD drive voltage can be provided to the mask ROM model by mask option. <6> Can operate on the subsystem clock. Table 12-1 shows the maximum number of pixels that can be displayed in each display mode. Table 12-1. Maximum Number of Pixels for Display Bias - 1/2 Time Division Static 2 3 1/3 3 4 Common Signal Used COM0 (COM0-COM3) COM0, COM1 COM0-COM2 COM0-COM2 COM0-COM3 160 (40 segments x 4 common)Note 4 Maximum Number of Pixels 40 (40 segments x 1 common)Note 1 80 (40 segments x 2 common)Note 2 120 (40 segments x 3 common)Note 3 Notes 1. Can display 5 digits with eight segments for each digit on an 8-segment LCD panel. 2. Can display 10 digits with four segments for each digit on an 8-segment LCD panel. 3. Can display 13 digits with three segments for each digit on an 8-segment LCD panel. 4. Can display 20 digits with two segments for each digit on an 8-segment LCD panel. 355 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (b) Setting of LCD controller/driver Set the LCD controller/driver as follows. When using the LCD controller/driver, set the watch timer in the operating status in advance. <1> Enables the watch operation by using the timer clock select register 2 (TCL2) and watch timer mode control register (TMC2). <2> Set the initial value to the display data memory (FA58H through FA7FH). <3> Specify the pins used for segment output by using the LCD display control register (LCDC). <4> Set the display mode and LCD clock by using the LCD display mode register. After that, set data to the display data memory according to the contents to be displayed. (c) LCD display data memory The LCD display data memory is mapped to addresses FA58H through FA7FH. The data stored to the LCD display data memory can be displayed on the LCD panel by using the LCD controller/driver. Figure 12-4 shows the relations between the contents of LCD display data memory and the segment/common outputs. The area not used for display can be used as an ordinary RAM area. Figure 12-4. Relations between Contents of LCD Display Data Memory and Segment/Common Output Address FA7FH FA7EH FA7DH FA7CH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 S0 S1 S2 S3 FA5AH FA59H FA58H S37/P82 S38/P81 S39/P80 COM3 COM2 COM1 COM0 Caution The high-order 4 bits of the LCD display data memory are not used as memory bits. Be sure to clear these bits to 0. 356 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (d) Common and segment signals Each pixel on an LCD panel lights when the potential difference between the corresponding common and segment signals reaches to a specific level (LCD drive voltage VLCD). Because an LCD panel degrades if DC voltages are applied as common and segment signals, it is driven by AC voltages. <1> Common signal The common signal is selected as shown in Table 12-2 according to the set number of time divisions and repeatedly operates in the cycles shown in the table. In the static mode, the same signal is output to COM0 through COM3. In the 2-time division mode, open the COM2 and COM3 pins. Open the COM3 pin in the 3-time division mode. Table 12-2. COM Signal COM Signal Number of Time Divisions Static COM0 COM1 COM2 COM3 2 time divisions Open Open 3 time divisions Open 4 time divisions <2> Segment signal Segment signals correspond to a 40-byte LCD display data memory (FA58H through FA7FH). Bits 0, 1, 2, and 3 of the display data memory are read in synchronization of COM0, COM1, COM2, and COM3, respectively. If the content of each bit is 1, the corresponding segment signal is converted to a select voltage and is output to the segment pin (S0 to S39). If the content of a bit is 0, the segment signal is converted to an unselect voltage. (Note that S24 through S39 are multiplexed with input/output port pins.) Therefore, confirm what combination of the front panel electrode (corresponding to a segment signal) and rear panel electrode (corresponding to a common signal) of the LCD panel generates a display pattern, and write the bit data corresponding to the pattern to be displayed on a one-to-one basis to the LCD display memory. In the static mode, bits 1, 2, and 3 of the LCD display data memory are not used for LCD display. In the 2- and 3-time division modes, bits 2 and 3, and bit 3 are not used for LCD display, respectively. These bits therefore can be used for any other purposes. Bits 4 through 7 are fixed to 0. 357 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER <3> Output waveforms of common and segment signals Only when the voltage levels of specific common and segment signals reach the select levels, VLCD (LCD drive voltage) level is reached and the corresponding pixel on the LCD panel lights. The pixel remains dark with any other combination of the common and segment signals. Figure 12-5 shows the waveform of the common signal, and Figure 12-6 shows the phase difference in voltage between the common and segment signals. Figure 12-5. Common Signal Waveform (a) Static display mode VLC0 VLCD VSS TF = T COMn (static) (b) 1/2 bias VLC0 COMn (2-time division) VLC2 VSS TF = 2T VLC0 COMn (3-time division) VLC2 VSS TF = 3T VLCD VLCD (c) 1/3 bias VLC0 VLC1 VLC2 VSS TF = 3T VLC0 VLC1 VLC2 VSS TF = 4T COMn (3-time division) VLCD COMn (4-time division) VLCD Remarks 1. T 2. TF : one cycle of LCDCL : frame frequency 3. VLCD : LCD drive voltage 358 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-6. Phase Difference in Voltage between Command Signal and Segment Signal (a) Static display mode Select Unselect VLC0 Common signal VSS VLC0 Segment signal VSS T T VLCD VLCD (b) 1/2 bias Select Unselect VLC0 Common signal VLC2 VSS VLC0 Segment signal VLC2 VSS T T VLCD VLCD (c) 1/3 bias Select Unselect VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS T T Common signal VLCD VLCD Segment signal Remarks 1. T : one cycle of LCDCL 2. VLCD : LCD drive voltage (e) Supplying LCD drive voltage The mask ROM model can be provided by mask option with a divider resistor that is used to create the LCD drive voltage (the PROM model is not provided with a divider resistor). By providing the divider resistor, an LCD drive voltage corresponding to each bias can be created without an external divider resistor. In addition, an LCD drive voltage can be supplied to the BIAS pin to support various LCD drive voltages. 359 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER 12.1 Static Display This section explains an example using the PD78064 subseries. A 4-digit static LCD is driven by using the 32 segment signals (S0 through S31) and a common signal (COM0). Figure 12-7 shows the display pattern and electrode wiring of the static LCD. Figure 12-8 shows the connections among the segment signals and common signal. Figure 12-9 shows an example of connecting an LCD driving power supply in the static display mode (with an external divider resistor, VDD = 5 V, and VLCD = 5 V). The display example in Figure 12-8 is "1234", and the contents of the display data memory (addresses FA60H through FA7FH) correspond to this. In this section, how to display the second digit, "3", is described. According to the display pattern in Figure 128, the select and unselect voltages must be output to the S8 through S15 pins in the timing of the common signal COM0, as shown in Table 12-3. Table 12-3. Select and Unselect Voltages (COM0) Segment Common COM0 S8 Unselect S9 Select S10 Select S11 Select S12 Unselect S13 Select S14 Unselect S15 Select From Table 12-3, it is clear that 10101110 must be set to bit 0 of the display data memory (addresses FA70H through FA77H) corresponding to S8 through S15. Figure 12-10 shows the LCD driving waveforms of S11, S12, and COM0. Because the same waveform as COM0 is output to COM1, 2, and 3, the driving capability can be increased by connecting COM0, 1, 2, and 3. Figure 12-7. Display Pattern and Electrode Wiring of Static LCD S8n + 3 S8n + 4 S8n + 2 S8n + 5 COM0 S8n + 6 S8n + 1 S8n S8n + 7 Remark n = 0-3 360 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-8. Connection of Static LCD DATA MEMORY ADDRESS FA7FH FA6FH C D C D A B E A B E 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 TIMING STROBE BIT0 BIT1 BIT2 BIT3 0 x x x 0 x x x 0 x x x 0 x x x 0 x x x 1 x x x 1 x x x 0 x x x 1 x x x 1 x x x 0 x x x 0 x x x 1 x x x 1 x x x 0 x x x 0 x x x 1 x x x 0 x x x 1 x x x 0 x x x 1 x x x 1 x x x 1 x x x 0 x x x 0 x x x 0 x x x 1 x x x 1 x x x 0 x x x 1 x x x 1 x x x 0 x x x Figure 12-9. Example of Connecting LCD Driving Power in Static Display Mode (with external divider resistor, VDD = 5 V, and VLCD = 5 V) S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 LIPS BIAS pin LEPS (= 0) VLC0 VLCD VLC2 S21 S20 S19 LCD PANEL S18 S17 VLC1 VSS VLCD = VDD S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 VDD S2 S1 S0 COM0 COM1 COM2 361 COM3 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-10. Example of Static LCD Driving Waveform TF VLC0 COM0 VSS Common signal VLC0 S11 VSS Segment signal VLC0 S12 VSS Segment signal + VLCD COM0-S11 0 LCD lights - VLCD + VLCD COM0-S12 0 LCD extinguishes - VLCD Remark TF: frame frequency To display the LCD, segment signals are output based on the waveform of the common signal. The static LCD is lit by a segment signal (S11) output at a frame frequency half a cycle shifted from that of the common signal (COM0) as shown in Figure 12-10. This means that a potential difference is generated between the common signal and segment signal, and this potential difference is responsible for lighting the LCD. As can be seen from COM0 and S11 in Figure 12-10, a potential difference VLCD (LCD drive voltage) is generated between these signals. To extinguish the LCD, the segment signal (S12) is output in a waveform synchronous to that of the common signal (COM0). In this way, the potential difference between COM0 and S12 is eliminated and the LCD remains dark. 362 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (1) Description of package * Subroutine name S_LCD : Static display data storage routine * Input parameter B_LCD : LCD display content storage buffer area * Data definition reference name S0 : LCD display data memory reference address (FA7FH) Name B_LCD i j WORKP Usage LCD display data storage buffer area Display digit loop counter Segment setting loop counter Display data storage area address saving area Attribute SADDR SADDR SADDR SADDRP Bytes 1 1 1 2 * LCD controller/driver * * * * OSMS = #00000001B ; Oscillation mode select register TCL2 = #xxx00xxxB ; Count clock of watch timer = selects system clock TMC2 = #0xxxxx1xB ; Supplies LCD clock (enables prescaler operation) LCDC = #01000010B ; LCD display control register (supplies LCD drive power from BIAS pin with segment pins S24 through S31 used) * LCDM = #10100100B ; LCD display mode register (sets static display, selects LCD clock, and turns on display) Caution Set the initial value to the LCD display data memory (FA58H through FA7FH) before turning on the LCD display. 363 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (2) Example of use EXTRN SLCD,B_LCD,S0 . . . ; Clears LCDRAM ; (from FA58H to FA7FH) ; ; ; ; ; ; ; ; ; ; ; ; ; ; Count clock of watch timer = selects main system clock Enables operation of prescaler Supplies LCD drive power from BIAS pin with segments S24 through 31 used Turns ON static display with 256-Hz clock selected HL=#S0 BC=#0FA80H-0FA58H while(BC!=#0) (AX) A=#0 [HL]=A HL-BC-endw ; B_LCD=#0 B_LCD+1=#0 B_LCD+2=#0 B_LCD+3=#0 ; TCL2=#00000000B TMC2=#00000010B LCDC=#01000010B LCDM=#10100100B ; . . B_LCD+3=A . . B_LCD+2=A . . B_LCD+1=A . . B_LCD=A CALL !S_LCD . . ; ; ; ; ; (3) SPD chart S_LCD Stores address S0 (RAM address of first digit of LCD) to HL register Stores B_LCD address (buffer area of first digit of LCD) - 1 to WORKP area (for: i = #0; i < #4; i + +) Increments WORKP area (display area address of next digit) Saves display data to A register by table reference (for: j = #0; j < #8; j + +) Shifts A register 1 bit to right and transfers bit 0 to CY Transfers CY to bit 0 of [HL] Decrements HL register (next segment address of LCD) 364 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (4) Program list PUBLIC S_LCD,B_LCD,S0 ; S0 EQU 0FA7FH ; 1st digit of LCD ; LCDRAM1 DSEG SADDR B_LCD: DS 4 ; Display BUF area i: DS 1 ; Work counter j: DS 1 ; Work counter LCDRAM2 DSEG SADDRP WORKP: DS 2 ; Work area ;****************************************************** ; LCD display (static display) processing ;****************************************************** LSDS CSEG S_LCD: HL=#S0 ; HL address S0 WORKP=#B_LCD-1 ; Work area address of B_LCD - 1 for(i=#0;i<#4;i++) ; DE=WORKP (AX) ; DE++ ; References display data of contents of next digit WORKP=DE (AX) ; X=[DE] (A) ; A=#0 ; AX+=#LCDDAT ; DE=AX ; A=[DE] ; for(j=#0;j<#8;j++) ; RORC A,1 ; Stores display data to bit 0 from address S0 [HL].0=CY ; HL-; next ; next ; RET ; LCDDAT: DB 11011110B ;0 DB 00000110B ;1 DB 11101100B ;2 DB 10101110B ;3 DB 00110110B ;4 DB 10111010B ;5 DB 11111010B ;6 DB 00011110B ;7 DB 11111110B ;8 DB 10111110B ;9 DB 01111110B ;A DB 11110010B ;B DB 11011000B ;C DB 11100110B ;D DB 11111000B ;E DB 01111000B ;F DB 00000000B ; Extinguishes END 365 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER 12.2 4-Time Division Display This section explains an example using the PD78064 subseries. Four LCD digits are driven by means of 1/3 bias and 4-time division by using the 16 segment signals (S0 through S15) and four common signals (COM0 through COM3). Figure 12-12 shows the connection of a 4-time division 4-digit LCD panel with 10 display patterns shown in Figure 12-11 and the segment (S0 through S15) and common (COM0 through COM4) signals of the PD78064 subseries. Figure 12-13 shows an example of connecting an LCD drive power supply in the 4-time division display mode (with external divider resistor, VDD = 5 V, and VLCD = 5 V). The display example in Figure 12-12 is "12345678", and the contents of the display data memory (addresses FA70H through FA7FH) correspond to this. In this case, "6" at the third digit has been taken as an example. According to the display pattern in Figure 1212, the select and unselect voltages shown in Table 12-4 must be output to the S4 and S5 pins in the timing of the common signals COM0 through COM3. Table 12-4. Select and Unselect Voltages (COM0, 1, 2, 3) Segment Common COM0 COM1 COM2 COM3 Select (a) Unselect (b) Select (c) Unselect (d) Select (e) Select (f) Select (g) Select (h) S4 S5 Remark (a) through (h) in the table corresponds to the segments a through h in Figure 12-12. Table 12-4 indicates that 0101 should be stored to the display data memory address (FA7BH) corresponding to S4. Figure 12-14 shows the LCD drive waveforms between S4 and COM0 and COM1 signals. Figure 12-11. Display Pattern of 4-Time Division LCD and Electrode Wiring S2n COM0 COM1 COM2 COM3 S2n + 1 Remark n = 0-7 366 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-12. Connections of 4-Time Division LCD Panel DATA MEMORY ADDRESS FA7FH TIMING STROBE C D A B E 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 BIT0 BIT1 BIT2 BIT3 Figure 12-13. Example of Connecting LCD Drive Power in 4-Time Division Mode (with external divider resistor, VDD = 5 V, VLCD = 5 V) S15 S14 S13 S12 S11 LEPS (= 0) VLC0 R VLC1 VLCD VLC2 R VSS R S10 LIPS S9 S8 LCD PANEL VLCD = VDD S7 S6 S5 S4 S3 S2 S1 S0 COM0 COM1 COM2 COM3 a e g h d f b c VDD BIAS pin 367 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER Figure 12-14. Example of 4-Time Division LCD Driving Waveform TF VLC0 COM0 VLC1 VLC2 VSS VLC0 COM1 VLC1 VLC2 VSS VLC0 COM2 VLC1 VLC2 VSS VLC0 COM3 VLC1 VLC2 VSS VLC0 S4 VLC1 VLC2 VSS Select Unselect Select Unselect + VLC0 + 1/3VLCD COM0-S4 0 - 1/3VLCD - VLCD + VLC0 + 1/3VLCD COM1-S4 0 - 1/3VLCD + VLCD Remarks 1. TF: frame frequency 2. The valid waveform of each common signal is enclosed in dotted line. 368 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER For 4-time division LCD display, the valid timing (enclosed in dotted line in Figure 12-14) of each common signal is output in a cycle 1/4 of the frame frequency (TF) as shown in Figure 12-14. In this timing,each segment signal is output to light or extinguish the LCD. For example, segment signal S4 outputs a waveform that lights the LCD in the timing of COM0 and COM2, in respect to each common signal (COM0 through COM3) in Figure 12-14. When the relations between each common signal and S4 is examined, it can be seen that a potential difference of VLCD (LCD drive voltage) is generated at the COM0 select timing between COM0 and S4, as can be seen from the waveform of COM0-S4. In the case of COM2 and S4, a voltage difference of VLCD (LCD drive voltage) is also generated between COM2 and S4 at the COM2 select timing. Therefore, the segment indicated by COM0, COM2 and S4 lights. Because a voltage difference between COM1 and S4 is always 1/3 VLCD (COM1-S4 in Figure 12-14) at the select timing of COM1 (COM1 in Figure 12-14), the LCD remains dark. 369 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (1) Description of package * Subroutine name S_4LCD : 4-time division display data storage routine * Input parameter B_LCD : LCD display content storage buffer area * Data definition reference name S0 : LCD display data memory reference address (FA7FH) Name B_LCD i WORKP Usage LCD display data storage buffer area Display digit loop counter Display data storage area address saving area Attribute SADDR SADDR SADDRP Bytes 1 1 2 * LCD controller/driver * * * * OSMS = #00000001B ; Oscillation mode select register TCL2 = #xxx00xxxB ; Count clock of watch timer = selects system clock TMC2 = #0xxxxx1xB ; Supplies LCD clock (enables operation of prescaler) LCDC = #00000001B ; LCD display control register (LCD driving power is supplied from VDD with segment signal pins S24 through S31 not used) * LCDM = #10100000B ; LCD display mode register (sets 4-time division display, selects LCD clock, turns ON display) Caution Set the initial value to the LCD display data memory (FA58H through FA7FH) before turning ON the LCD. 370 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (2) Example of use EXTRN S_4LCD,B_LCD,S0 . . . HL=#S0 BC=#0FA80H-0FA58H while(BC!=#0) (AX) A=#0 [HL]=A HL-BC-endw B_LCD=#0 B_LCD+1=#0 B_LCD+2=#0 B_LCD+3=#0 ; TCL2=#00000000B TMC2=#00000010B LCDC=#00000001B LCDM=#10100000B ; . . B_LCD+3=A . . B_LCD+2=A . . B_LCD+1=A . . B_LCD=A CALL !S_4LCD . . ; ; ; ; Count clock of watch timer = selects main system clock Enables prescaler operation Supplies driving power from VDD with segments S24 through S31 not used Turns on 4-time division display with 256-Hz clock selected, turns ON display ; Clears LCDRAM ; (from FA58H to FA7FH) ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; (3) SPD chart S_4LCD Stores address S0 (RAM address of first digit of LCD) to HL register Stores address B_LCD (buffer area of first digit of LCD) - 1 to WORKP area (for: i = #0; i < #8; i + +) Increments WORKP area (display area address of next digit) Stores display data to A register by table reference Rotates address [HL] 1 digit to left (transfers low-order 4 bits of A register to low-order 4 bits of address [HL]) Shifts A register 4 bits to right Decrements HL register (LCD RAM area corresponding to odd segments of one digit of LCD) Rotates address [HL] 1 digit to left Decrements HL register (LCD RAM area corresponds to even segment of 1 digit of LCD) 371 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER (4) Program list PUBLIC S0 S_4LCD,B_LCD,S0 EQU 0FA7FH ; 1st digit of LCD LCD4RAM1 DSEG SADDR ; Display BUF area B_LCD: DS 8 ; Work counter i: DS 1 LCD4RAM2 DSEG SADDRP ; Work area WO4RKP: DS 2 ;*************************************************************** ; LCD display (4-time division display) processing ;*************************************************************** LSD4 CSEG S_4LCD: ; HL address S0 HL=#S0 ; WORKP=#B_LCD-1 ; for(i=#0;i<#8;i++) ; DE=WORKP (AX) ; References display data of contents of next digit DE++ ; WORKP=DE (AX) ; X=[DE] (A) ; A=#0 ; AX+=#LCDDAT ; DE=AX ; A=[DE] ; [HL] low-order 4 bits of A register ROL4 [HL] ; Shifts high-order 4 bits of A register to lower 4 bits A >>= 1 ; A >>= 1 ; A >>= 1 ; A >>= 1 ; HL- - HL-; [HL] low-order 4 bits of A register ROL4 [HL] ; HL- - HL-; next ; RET LCDDAT: ;0 DB 11010111B ;1 DB 00000110B ;2 DB 11100011B ;3 DB 10100111B ;4 DB 00110110B ;5 DB 10110101B ;6 DB 11110101B ;7 DB 00010111B ;8 DB 11110111B ;9 DB 10110111B ;A DB 01110111B ;B DB 11110100B ;C DB 11010001B ;D DB 11100110B ;E DB 11110001B ;F DB 01110001B ; Extinguishes DB 00000000B END 372 CHAPTER 13 APPLICATIONS OF KEY INPUT This chapter introduces an example of a program that inputs signals from a key matrix of 4 x 8 keys. The key scan be pressed successively, and two or more keys can be pressed simultaneously. In the circuit shown in this section, the high-order 4 bits of port 3 (P34 through P37) are used as key scan signals, and port 4Note is used as key return signals. As the pull-up resistor of port 4 for key return, the internal pull-up resistor set by software is used (refer to Figure 13-1). Port 4 of the 78K/0 series has a function to detect the falling edges of the eight port pins in parallel. If port 4 is used for key return signals, therefore, the standby mode can be released through detection of a falling edge, i.e., by key input. In this example, the PD78054 subseries is used. Note With the PD78064, 78064Y, 780308, 780308Y, and 78064B subseries, port 11 is used instead of port 4. Figure 13-1. Key Matrix Circuit PD78054 P34 P35 P36 P37 Pull-up resistors connected P40 P41 P42 P43 P44 P45 P46 P47 = The input keys are stored to RAM on a one key-to-1 bit basis. The RAM bit corresponding to a pressed key is set and the bit corresponding to a released key is cleared. By testing the RAM data on a 1-bit-by-1-bit basis starting from the first bit, the key status can be checked. To absorb chattering, the key is assumed to be valid when four successive key codes coincide with a given code. For example, if a key code is sampled every 5 ms, chattering of 15 ms to 20 ms can be absorbed. If the key input is changed, a key change flag (KEYCHG) is set. 373 CHAPTER 13 APPLICATIONS OF KEY INPUT (1) Description of package Name KEYDATA WORK CHATCT WORKCT Stores valid key data Stores key data during chattering Chattering counter Loop processing work counter 1 Usage Attribute SADDR Bytes 4 Name CHGFG KEYCHG CHTEND Usage Set if key input changes Set if valid key changes Confirms end of chattering * P4 * P3 (P34-P37) * PUO4 = 1 ; Connects pull-up resistor to P4 * PM3 = #0000xxxxB ; Sets high-order 4 bits of P3 in output mode * Call KEYIN at specific intervals. * Before inputting the key data, test the key change flag. The key change flag is not cleared by the subroutine. Clear the flag after it has been tested. 374 CHAPTER 13 APPLICATIONS OF KEY INPUT (2) Example of use EXTRN EXTBIT VETM3 CSEG DW KEYDATA,CHATCT,KEYIN KEYCHG AT 1EH INTTM3 ; Sets vector address of watch timer MAINDAT DSEG SADDR CT5MS: DS 1 . . . . TMC2=#00100110B CLR1 TMMK3 CT5MS=#3 PM3=#00000000B SET1 PUO.4 CHATCT=#3 . . . . if_bit(KEYCHG) CLR1 KEYCHG ; Key input processing endif . . . . ;********************************************** ; Watch timer interrupt processing ; Interval time: 1.95 ms ;********************************************** INTTM3: . . . . DBNZ CT5MS,$RTNTM3 MOV CT5MS,#3 CALL !ANKEYIN RTNTM3: . . . . RETI ; Sets P3 in output mode ; Pulls P4 up ; Initial setting of chattering counter ; Key changed? ; 1.95 ms interrupt ; 1.95 ms x 3 elapses 375 CHAPTER 13 APPLICATIONS OF KEY INPUT (3) SPD chart KEYIN Outputs key scan signal to P34-P37 UNTIL: key scan signal output ends Key return signal input from P4 IF: key input changes THEN Sets status in which key input changes CHTFG Shifts key scan signal 1 bit IF: no key input change THEN IF: chattering being absorbed THEN IF: chattering ends THEN IF: valid key changes THEN Sets key change status Sets KEYCHG Updates key data ELSE Sets chattering absorption start status Clears CHTEND 376 CHAPTER 13 APPLICATIONS OF KEY INPUT (4) Program list PUBLIC KEY_DAT DSEG KEYDATA:DS WORK: DS CHATCT: DS WORKCT: DS KEY_FLG CHGFG KEYCHG CHTEND BSEG DBIT DBIT DBIT KEYDATA,KEYCHG,KEYIN,CHATCT SADDR 4 4 1 1 ; Key data storage area ; Chattering key data ; Chattering counter ; Key change status ; Key changed ; Chattering absorption end status KEY_SEG CSEG ;******************************* * Matrix key input ;******************************* KEYIN: CLR1 CHGFG P3&=#00001111B P3|=#00010000B HL=#WORK repeat A=P4 A^=#11111111B if(A!=[HL]) SET1 CHGFG [HL]=A endif HL++ A=P3 A&=#11110000B X=A A=P3 A+=X P3=A until_bit(CY) if_bit(!CHGFG) if_bit(!CHTEND) CHATCT-if(CHATCT==#0) SET1 CHTEND DE=#WORK HL=#KEYDATA for(WORKCT=#0;WORKCT<#4;WORKCT++) if([DE]!=[HL]) (A) SET1 KEYCHG endif A<->[HL] HL++ DE++ next endif endif else CHATCT=#3 CLR1 CHTEND endif RET ; Sets address of key work area ; Data inverted ; Key changed? ; Shifts key scan 1 bit ; Key changed ; Chattering absorbed ; Chattering ends ; Key changed ; Transfers WORK to KEYDATA 377 [MEMO] 378 APPENDIX A DESCRIPTION OF SPD CHART SPD stands for Structured Programming Diagrams. Structuring means structuring the logical processing of a program, and designing and formulating the logic by using the basic structure of the logic elements. All programs can be created by only combining the basic structure of logic elements, (sequentially, selectively, or repeatedly). (This is called a structured theorem). Through structuring, the flow of a program is clarified, and the reliability is improved. Although various methods are available for expressing the structuring of a program, NEC employs a diagram technique called SPD. The following table describes the SPD symbols used for the SPD technique and compares them with flowchart symbols. Table A-1. Comparison between SPD Symbols and Flowchart Symbol (1/2) Processing Name Sequential processing SPD Symbol Flowchart Symbol Processing 1 Processing 2 Processing 1 Processing 2 Conditional branch (IF) (IF: condition) [THEN] Processing 1 [ELSE] Processing 2 Condition THEN Processing 1 ELSE Processing 2 Conditional branch (SWITCH) (SWITCH: condition) [CASE: 1] Processing 1 [CASE: 2] . . . Processing 2 Processing 1 Processing 2 Processing n Condition [CASE: n] Processing n 379 APPENDIX A DESCRIPTION OF SPD CHART Table A-1. Comparison between SPD Symbols and Flowchart Symbol (2/2) Processing Name Conditional loop (WHILE) (WHILE: condition) Processing Condition THEN Processing ELSE SPD Symbol Flowchart Symbol Conditional loop (UNTIL) (UNTIL: condition) Processing ELSE Condition THEN Conditional loop (FOR) Initial value Processing (FOR: initial value; condition; increment/decrement specification) Processing Condition THEN Processing Increment/ decrement ELSE Infinite loop (WHILE: forever) Processing Processing Connector (IF: condition) [THEN] GOTO A Condition THEN A Processing ELSE A A Processing 380 APPENDIX A DESCRIPTION OF SPD CHART 1. Sequential processing Sequential processing executes processing from top to bottom in the sequence in which processing appears. * SPD chart Processing 1 Processing 2 2. Conditional branch: 2 branch (IF) Processing contents are selected according to the condition specified by IF is true or false (THEN/ELSE). * SPD chart (IF: condition) [THEN] Processing 1 [ELSE] Processing 2 Example 1. Identification of positive or negative of X (IF: X > 0) [THEN] X is positive number [ELSE] X is 0 or negative number 2. STOP if signal is red (IF: signal = red) [THEN] STOP 381 APPENDIX A DESCRIPTION OF SPD CHART 3. Conditional branch: multiple branch (SWITCH) The condition specified by SWITCH is compared with the status indicated by CASE to select the processing. The processing of the SWITCH statement may be executed only when the given values coincide, or continued downward starting from when the given values coincide (if the processing is not continued downward, `break' is described). If there is no coincide status, `default' processing is executed (description of `default' is arbitrary). (1) Execution only on coincidence * SPD chart (execution) (SWITCH: condition) [CASE: status 1] Processing 1 break [CASE: status 2] Processing 2 . . . break . . . Processing n [default] Processing 0 If status does not coincide: processing 0 When status 2: processing 2 . . . . . . . . . . When status 1: processing 1 [CASE: status n] When status n: processing n Example Displays name of month by input characters (SWITCH: input character) [CASE: '1'] Displays Jan break [CASE: '2'] Displays Feb . . . [default] Displays ERROR break . . . 382 APPENDIX A DESCRIPTION OF SPD CHART (2) If processing continues from coincidence status * SPD chart (execution) (SWITCH: condition) [CASE: Status 1] Processing 1 [CASE: Status 2] . . . Processing 2 . . . Processing n [default] Processing 0 If status does not coincide: processing 0 When status 2: processing 2 ... processing n . . . . . . . . . . When status n: processing n When status 1: processing 1 processing 2 ... processing n [CASE: Status n] Example Transmission/reception of serial interface (execution) (SWITCH: transfer mode) [CASE: 1] Address transmission [CASE: 2] Data transmission break [CASE: 3] Data reception When status 3: data reception When status 2: data transmission When status 1: address transmission data transmission 4. Conditional Loop (WHILE) The condition indicated by WHILE is judged. If the condition is satisfied, processing is repeatedly executed (if the condition is not satisfied from the start, the processing is not executed). * SPD chart (WHILE: condition) Processing Example Buffers key until RETURN key is input (WHILE: not RETURN key) Inputs 1 character key Stores input key to buffer 383 APPENDIX A DESCRIPTION OF SPD CHART 5. Conditional Loop (UNTIL) The condition indicated by UNTIL is judged after processing has been executed, and the processing is repeatedly executed until a given condition is satisfied (even if the condition is not satisfied from the start, the processing is executed once). * SPD chart (UNTIL: condition) Processing Example Multiplies value of B register by 10 and stores result to A register Initializes A register Sets value to B register Stores 10 to counter (UNTIL: counter = 0) A=A+B Decrements counter 6. Conditional Loop (FOR) While the condition of the parameter indicated by FOR is satisfied, processing is repeatedly executed. * SPD chart (FOR: initial value; condition; increment/decrement specification) Processing Example Clears 256 bytes to 0 starting from address HL Sets first address to HL register (FOR: WORKCT = #0; WORKCT < #256; WORKCT + +) Clears address HL to 0 Increments HL register 384 APPENDIX A DESCRIPTION OF SPD CHART 7. Infinite Loop If `forever' is set as the condition of WHILE, processing is infinitely executed. * SPD chart (WHILE: forever) Processing Example To execute main processing repeatedly (WHILE: forever) Decodes key Stores key code to display area Main processing 8. Connector (GOTO) Unconditionally branches to a specified address. * SPD chart (1) To branch to same module (IF: condition) [THEN] . . . ERR Processing GOTO ERR 385 APPENDIX A DESCRIPTION OF SPD CHART (2) To branch to different module (IF: condition) [THEN] GOTO ERR (SUB_ER) ; Module name SUB_ER Processing . . . ERR Processing Example To select a parameter at the start address of a subroutine and set wait state WAIT10 WAIT20 WAIT30 WAIT Sets 10 to A register GOTO WAIT Sets 20 to A register GOTO WAIT Sets 30 to A register (UNTIL: A = 0) Decrements A 9. Connector (continuation) Used when the SPD of one module requires two or more pages to indicate the flow of processing. * SPD chart Processing 1 1 Processing 2 Processing 3 1 Processing 4 386 APPENDIX B REVISION HISTORY The revision history of this document is as follows. "Chapter" indicates the chapter number in the preceding edition. (1/2) Edition 2nd edition Major Revision from Preceding Edition Addition of following products as target products: PD780018, 780018Y, 780058, 780058Y, 780308, 780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY, 78098B subseries, PD78070A, 78070AY PD78052(A), 78053(A), 78054(A) PD78062(A), 78063(A), 78064(A) PD78081(A), 78082(A), 78P083(A), 78081(A2) PD78058F(A), 78058FY(A) PD78064B(A) Deletion of following products as target products: PD78P054Y, 78P064Y, 78074, 78075, 78074Y, 78075Y Addition of Note 2 and Caution 2 to Figure 4-5 Format of Watchdog Timer Mode Register Addition of Caution to Figure 5-8 Format of External Interrupt Mode Register 0 Addition of Table 8-2 Items Supported by Each Subseries Addition of Table 8-3 Registers of Serial Interface Addition of note on using wake-up function and note on changing operation mode to Figures 8-7 and 8-8 Format of Serial Operating Mode Register 0 Addition of Caution to Figures 8-16 and 8-17 Format of Automatic Data Transmission/Reception Interval Specification Register Addition of Figures 8-23 and 8-24 Format of Serial Interface Pin Select Register CHAPTER 4 APPLICATION OF WATCHDOG TIMER CHAPTER 5 APPLICATION OF 16-BIT TIMER/EVENT COUNTER CHAPTER 8 APPLICATION OF SERIAL INTERFACE Throughout Chapter PD6252 as maintenance product in 8.1 Interface with EEPROMTM (PD6252) Addition of (5) Limitations when using I2C bus mode to 8.1.2 Communication in I2C bus mode Addition of (f) Limitations when using UART mode to 8.5 Interface in Asynchronous Serial Interface (UART) Mode 387 APPENDIX B REVISION HISTORY (2/2) Edition 2nd edition Major Revision from Preceding Edition Description of following register formats and tables for each subseries: Figures 8-14 and 8-15 Format of Automatic Data Transfer/ Reception Control Register Tables 8-4, 8-5, and 8-6 Setting of Operating Modes of Serial Interface Channel 2 Figures 12-1 and 12-2 Format of LCD Display Mode Register Addition of Figure 11-3 Format of Port Mode Register 12 Chapter CHAPTER 8 APPLICATION OF SERIAL INTERFACE CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT CHAPTER 12 APPLICATION OF LCD CONTROLLER/DRIVER Description of following register formats for each subseries: Figures 12-1 and 12-2 Format of LCD Display Mode Register 388 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-889-1689 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Corporation Semiconductor Solution Engineering Division Technical Information Support Dept. Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 96.8 Excellent Good Acceptable Poor |
Price & Availability of UPD78081CU-XXX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |